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Comparison of Discrete- and Continuous Time Sigma-Delta Converters Anti-Aliasing Filter Explicit anti-aliasing filter (AAF) required Sampling Sampling at input low jitter & full linearity required for sampler Max. frequency and bandwidth of opamps Discrete-Time Continuous-Time All transients must settle within half of clock cycle, quickly changing pulses everywhere in circuit high bandwidth requirements limit max. frequency Stephan Henzler Mixed-Signal-Electronics 2012/13 Implicit filtering AAF may be obsolete for some applications Sampling at comparator, i.e. within ∑∆-loop sampling error subject to noise shaping Continuous time waveforms 5-10x relaxed bandwidth requirements higher clock frequency possible 314
Comparison of Discrete- and Continuous Time Sigma-Delta Converters Jitter Only critical for sampler but not for rest of sigma delta modulator Discrete-Time Continuous-Time Stephan Henzler Mixed-Signal-Electronics 2012/13 Very sensitive to timing variations of clock Loopdelay Not an issue Very sensitive to loop delay Switches Signal dependant on resistance Signal dependant comparator delay No switches Not an issue Very sensitive causes harmonic distortion 315
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Mixed-Signal-Electronics PD Dr.-Ing
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Stephan’s ambition for this cours
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Administratives Lecture: Stephan He
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The Macroscopic World is Purely Ana
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Topics of MSE Course Structure of
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Recommended Literature Analog Integ
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Constraints of Mixed Signal Circuit
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Generic Structure of Mixed-Signal S
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Representation of Discrete Time Sig
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Inverse Z-Transformation Methods f
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Representation of Discrete Time Sig
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low-pass low-pass low-pass Aliasing
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amplitude fsampling = 1 f signal,2
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Anti Aliasing Filter No brick wall
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Practical Sampling: Sample & Hold
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Xsh(!) = ¡ 1 j!¿ Sampling with Fi
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generalization X(s) = Relation Betw
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Downsampling II Mathematically dow
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Upsampling Stephan Henzler Mixed-Si
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Fractional Sample Rate Conversion
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Example for Simple Anti Aliasing Fi
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Transistor Description (for hand ca
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Chapter 2 Sample and Hold Circuits
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Sample & Hold Circuit Stephan Henzl
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Sample & Hold: Clock Feed-Through 3
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5. 6. Clock jitter Sample & Hold Ci
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Impact of Jitter on S&H Performance
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Noise due to jitter: Jitter Effect
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S&H with Correlated Double Sampling
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Noise of Sampled Signals: kT/C-Nois
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Closed Loop Track & Hold Circuit 1
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Closed Loop Track & Hold Circuit 3
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Summary Sample & Hold Circuits Step
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Resistor Realizations in MOS Techno
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Resistor Realizations in MOS Techno
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Switched Capacitor Resistor Emulati
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Resistor Equivalents Stephan Henzle
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Parameter Variations in SC Circuits
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Implementation of Integrated Capaci
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Vertical Parallel Plate Capacitor S
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Limitations of SC-Equivalence Steph
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Limitations of SC-Equivalence Switc
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Switched Capacitor Integrators Step
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z-Transformation Approximation on
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Analysis of Switched-Capacitor Circ
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Impact of Parasitic Capacitances C
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Switched Capacitor Amplifier Stepha
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SC Amplifier: Output Signal Stephan
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Superposition Theorem in SC Circuit
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Ideal Digital-to-Analog Conversion
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DAC Gain Error Stephan Henzler Mixe
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Ideal Analog-to-Digital Conversion
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Quantization in A/D-Converters Step
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Quantization in A/D-Converters Sig
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ADC Gain Error Stephan Henzler Mixe
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Non-Linearity in Data Converters St
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Nonlinearity in Data-Converters Ste
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DAC Nonlinearity: Differential Nonl
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ADC Nonlinearity: Integral Nonlinea
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Dynamic ADC Measurement ADC conver
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Harmonic Distortion Caused by Nonli
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Effective Number of Bits An ideal
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Other Useful Figures in Mixed-Signa
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Non-Linearity Gain Compression Co
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Superposition of Two Frequencies St
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Non-Linearity Cross Modulation Co
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Non-Linearity Intermodulation Two
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Non-Linearity: Further Reading Rec
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Chapter 5 Nyquist Rate Digital-to-A
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max value bus voltage follower stri
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Elmore Delay (cont.): Path Resistan
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Elmore Delay (cont): Delay Approxim
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Stephan Henzler Mixed-Signal-Electr
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Normalized Delay 300 250 200 150 10
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Stephan Henzler Mixed-Signal-Electr
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Monotonicity in Binary Weighted DAC
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Implementation of Binary Weighted D
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High number of bits - large area Hi
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R-2R-Ladder Network Stephan Henzler
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SC-Amplifier with Controllable Capa
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Thermometer Code Converters (method
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Hybrid Converter Architectures Step
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Charge Scaling DAC Compatibel with
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Analog-to-Digital Converter Familie
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Dual-Slope Analog-to-Digital Conver
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Iterative Analog-to-Digital Convert
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Converter with Successive Approxima
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Converter with Successive Approxima
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Modified SAR Algorithm Stephan Henz
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Charge Redistribution SAR Converter
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Charge Redistribution SAR Converter
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Hybrid SAR Converters Search can b
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Detailed SAR Architecture Let’s
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Binary Weighted SAR Stephan Henzler
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Algorithmic Analog-to-Digital Conve
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Illustration in Robertson Diagram 2
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Voltage Doubling in Algorithmic Con
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Voltage Doubling in Algorithmic Con
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Pipelined ADC 1 Going for pipeline
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High-Speed ADC: Pipeline Processing
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Impact of Comparator Offset on ADC
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Impairments in SAR Algorithms Find
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Redundant SAR Algorithms Stage qua
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Subranging Principle quantization e
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Linear Model of Subranging ADC Step
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Linear Model of Subranging ADC Eff
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General Pipeline SAR ADC Stephan He
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Background Calibration for Stage Ga
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Summary Pipeline ADC Stage errors
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implemented as parallel connection
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thermometer code one-hot code trans
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Bubble Correction in Flash Converte
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Interpolating Flash Converter Steph
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Kickback Effect Especially in flas
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Folding ADC: Operation Principle St
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High-Speed ADC: Parallel Processing
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Chapter 7 Comparators Stephan Henzl
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Static Characteristics of Comparato
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Operational Amplifier as Comparator
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Comparator Propagation Delay Linea
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Track & Latch Circuit I Stephan Hen
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Principle of Track-and-Latch Stage
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Latched Comparators I Standard arc
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Track & latch circuit: Latched Comp
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Current Mode (CML) Latch Combines
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Elimination of Memory Effect Prech
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Chapter 8 Oversampled Converters Si
Page 263 and 264: Linear Model of Quantization Noise
Page 265 and 266: Quantization Noise and Oversampling
Page 267 and 268: Feasibility of Oversampling Goal:
Page 269 and 270: First Order Noise Shaping Stephan H
Page 271 and 272: First Order Noise Shaping Stephan H
Page 273 and 274: Calculation of Signal-to-Noise Rati
Page 275 and 276: SC Implementation of 1. Order ΣΔ
Page 277 and 278: Comparison Nyquist Rate vs. SD AD N
Page 279 and 280: Calculation of Transfer Functions S
Page 281 and 282: Simulation with Matlab/Simulink Ste
Page 283 and 284: Output Spectrum of ΣΔ-Modulator f
Page 285 and 286: Input Level Dependent SNR 2. Order
Page 287 and 288: Tones Stephan Henzler Mixed-Signal-
Page 289 and 290: Dithering Reduce the risk of tones
Page 291 and 292: maximum noise peak Tones input DC l
Page 293 and 294: STF of 3. Order ΣΔ-Modulator Step
Page 295 and 296: Cascaded ΣΔ-Modulator (Multi stAg
Page 297 and 298: 3. Order MASH Structure Stephan Hen
Page 299 and 300: hist(S1) 12000 10000 8000 6000 4000
Page 301 and 302: hist(S1) 2.5 2 1.5 1 0.5 0 -1 -0.8
Page 303 and 304: ΣΔ-Analog-to-Digital Conversion S
Page 305 and 306: Sinc-Filter Basic low-pass filter a
Page 307 and 308: Sinc Filter Transfer Functions Step
Page 309 and 310: Implementation of Sinc-Filter Steph
Page 311 and 312: ΣΔ-Digital-to-Analog Conversion S
Page 313: Continuous Time Sigma-Delta Convert
Page 317: Web References Murmann. VLSI Data
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