Here - TUM

Summary Pipeline ADC
Stage errors can be tolerated if the residue stays inside the
convergence region
– Minimum requirement is that the residue is back in the convergence region
before the final quantizer)
– Take care for nonlinearity which is not revealed by the linear model
Trade-off sampling frequency – resolution – latency
Number of stages, i.e. number of elements grows linearly
with resolution (not exponentially, ref flash ADC)
Accurate sample-and-hold elements required
(That’s the reason why pipelined time-to-digital converters do not exist)
Stephan Henzler Mixed-Signal-Electronics 2012/13
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