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General Pipeline SAR ADC II As long as analog and digitals gains match all intermediate terms vanish Resolution R: Gain elements determine resolution, not the stage quantizers Effective stage resolution: Last stage must not saturate under all circumstances! Stephan Henzler Mixed-Signal-Electronics 2012/13 222
Background Calibration for Stage Gain Stephan Henzler Mixed-Signal-Electronics 2012/13 Digital gain is continuously adjusted, i.e. even slow transient variations are corrected Li et al., Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy, TCAS II, 9/2003. Fu et al., A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters, JSSC, 12/1998 Liu et al., A 15b 40MS/s CMOS Pipelined ADC with Digital Background Calibration, JSSC, 5/2005 many more … 223
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Mixed-Signal-Electronics PD Dr.-Ing
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Stephan’s ambition for this cours
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Administratives Lecture: Stephan He
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The Macroscopic World is Purely Ana
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Topics of MSE Course Structure of
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Recommended Literature Analog Integ
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Constraints of Mixed Signal Circuit
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Generic Structure of Mixed-Signal S
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Representation of Discrete Time Sig
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Inverse Z-Transformation Methods f
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Representation of Discrete Time Sig
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low-pass low-pass low-pass Aliasing
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amplitude fsampling = 1 f signal,2
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Anti Aliasing Filter No brick wall
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Practical Sampling: Sample & Hold
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Xsh(!) = ¡ 1 j!¿ Sampling with Fi
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generalization X(s) = Relation Betw
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Downsampling II Mathematically dow
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Upsampling Stephan Henzler Mixed-Si
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Fractional Sample Rate Conversion
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Example for Simple Anti Aliasing Fi
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Transistor Description (for hand ca
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Chapter 2 Sample and Hold Circuits
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Sample & Hold Circuit Stephan Henzl
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Sample & Hold: Clock Feed-Through 3
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5. 6. Clock jitter Sample & Hold Ci
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Impact of Jitter on S&H Performance
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Noise due to jitter: Jitter Effect
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S&H with Correlated Double Sampling
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Noise of Sampled Signals: kT/C-Nois
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Closed Loop Track & Hold Circuit 1
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Closed Loop Track & Hold Circuit 3
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Summary Sample & Hold Circuits Step
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Resistor Realizations in MOS Techno
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Resistor Realizations in MOS Techno
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Switched Capacitor Resistor Emulati
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Resistor Equivalents Stephan Henzle
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Parameter Variations in SC Circuits
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Implementation of Integrated Capaci
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Vertical Parallel Plate Capacitor S
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Limitations of SC-Equivalence Steph
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Limitations of SC-Equivalence Switc
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Switched Capacitor Integrators Step
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z-Transformation Approximation on
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Analysis of Switched-Capacitor Circ
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Impact of Parasitic Capacitances C
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Switched Capacitor Amplifier Stepha
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SC Amplifier: Output Signal Stephan
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Superposition Theorem in SC Circuit
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Ideal Digital-to-Analog Conversion
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DAC Gain Error Stephan Henzler Mixe
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Ideal Analog-to-Digital Conversion
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Quantization in A/D-Converters Step
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Quantization in A/D-Converters Sig
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ADC Gain Error Stephan Henzler Mixe
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Non-Linearity in Data Converters St
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Nonlinearity in Data-Converters Ste
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DAC Nonlinearity: Differential Nonl
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ADC Nonlinearity: Integral Nonlinea
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Dynamic ADC Measurement ADC conver
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Harmonic Distortion Caused by Nonli
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Effective Number of Bits An ideal
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Other Useful Figures in Mixed-Signa
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Non-Linearity Gain Compression Co
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Superposition of Two Frequencies St
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Non-Linearity Cross Modulation Co
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Non-Linearity Intermodulation Two
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Non-Linearity: Further Reading Rec
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Chapter 5 Nyquist Rate Digital-to-A
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max value bus voltage follower stri
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Elmore Delay (cont.): Path Resistan
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Elmore Delay (cont): Delay Approxim
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Stephan Henzler Mixed-Signal-Electr
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Normalized Delay 300 250 200 150 10
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Stephan Henzler Mixed-Signal-Electr
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Monotonicity in Binary Weighted DAC
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Implementation of Binary Weighted D
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High number of bits - large area Hi
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R-2R-Ladder Network Stephan Henzler
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SC-Amplifier with Controllable Capa
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Thermometer Code Converters (method
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Hybrid Converter Architectures Step
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Charge Scaling DAC Compatibel with
Page 171 and 172: Analog-to-Digital Converter Familie
Page 173 and 174: Dual-Slope Analog-to-Digital Conver
Page 175 and 176: Iterative Analog-to-Digital Convert
Page 177 and 178: Converter with Successive Approxima
Page 179 and 180: Converter with Successive Approxima
Page 181 and 182: Modified SAR Algorithm Stephan Henz
Page 183 and 184: Charge Redistribution SAR Converter
Page 185 and 186: Charge Redistribution SAR Converter
Page 187 and 188: Hybrid SAR Converters Search can b
Page 189 and 190: Detailed SAR Architecture Let’s
Page 191 and 192: Binary Weighted SAR Stephan Henzler
Page 193 and 194: Algorithmic Analog-to-Digital Conve
Page 197 and 198: Illustration in Robertson Diagram 2
Page 201 and 202: Voltage Doubling in Algorithmic Con
Page 203 and 204: Voltage Doubling in Algorithmic Con
Page 205 and 206: Pipelined ADC 1 Going for pipeline
Page 207 and 208: High-Speed ADC: Pipeline Processing
Page 209 and 210: Impact of Comparator Offset on ADC
Page 211 and 212: Impairments in SAR Algorithms Find
Page 213 and 214: Redundant SAR Algorithms Stage qua
Page 215 and 216: Subranging Principle quantization e
Page 217 and 218: Linear Model of Subranging ADC Step
Page 219 and 220: Linear Model of Subranging ADC Eff
Page 221: General Pipeline SAR ADC Stephan He
Page 225 and 226: Summary Pipeline ADC Stage errors
Page 227 and 228: implemented as parallel connection
Page 229 and 230: thermometer code one-hot code trans
Page 231 and 232: Bubble Correction in Flash Converte
Page 233 and 234: Interpolating Flash Converter Steph
Page 235 and 236: Kickback Effect Especially in flas
Page 237 and 238: Folding ADC: Operation Principle St
Page 239 and 240: High-Speed ADC: Parallel Processing
Page 241 and 242: Chapter 7 Comparators Stephan Henzl
Page 243 and 244: Static Characteristics of Comparato
Page 245 and 246: Operational Amplifier as Comparator
Page 247 and 248: Comparator Propagation Delay Linea
Page 249 and 250: Track & Latch Circuit I Stephan Hen
Page 251 and 252: Principle of Track-and-Latch Stage
Page 253 and 254: Latched Comparators I Standard arc
Page 255 and 256: Track & latch circuit: Latched Comp
Page 257 and 258: Current Mode (CML) Latch Combines
Page 259 and 260: Elimination of Memory Effect Prech
Page 261 and 262: Chapter 8 Oversampled Converters Si
Page 263 and 264: Linear Model of Quantization Noise
Page 265 and 266: Quantization Noise and Oversampling
Page 267 and 268: Feasibility of Oversampling Goal:
Page 269 and 270: First Order Noise Shaping Stephan H
Page 271 and 272: First Order Noise Shaping Stephan H
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Calculation of Signal-to-Noise Rati
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SC Implementation of 1. Order ΣΔ
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Comparison Nyquist Rate vs. SD AD N
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Calculation of Transfer Functions S
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Simulation with Matlab/Simulink Ste
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Output Spectrum of ΣΔ-Modulator f
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Input Level Dependent SNR 2. Order
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Tones Stephan Henzler Mixed-Signal-
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Dithering Reduce the risk of tones
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maximum noise peak Tones input DC l
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STF of 3. Order ΣΔ-Modulator Step
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Cascaded ΣΔ-Modulator (Multi stAg
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3. Order MASH Structure Stephan Hen
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hist(S1) 12000 10000 8000 6000 4000
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hist(S1) 2.5 2 1.5 1 0.5 0 -1 -0.8
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ΣΔ-Analog-to-Digital Conversion S
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Sinc-Filter Basic low-pass filter a
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Sinc Filter Transfer Functions Step
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Implementation of Sinc-Filter Steph
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ΣΔ-Digital-to-Analog Conversion S
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Continuous Time Sigma-Delta Convert
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Comparison of Discrete- and Continu
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Web References Murmann. VLSI Data
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