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Binary Weighted Current Mode Converters Until now: All possible voltages are generated, 1 out of 2 N voltages is copied to the output 1 1 1 IF b1I b2I b3I b4I max 1 2 min Now: • Current mode, i.e. currents are generated, superposed and then converted into the output voltage • Input word is already binary generated binary weighted currents and superpose them into a current that corresponds to the input word. N I I scale switches Stephan Henzler Mixed-Signal-Electronics 2012/13 2 4 8 150
Monotonicity in Binary Weighted DACs Binary weighted converters are not necessarily monotonic Example: 1 0 1 2 1 1 4 1 1 8 1 1 0 0 0 1 Stephan Henzler Mixed-Signal-Electronics 2012/13 7 8 6 8 0 1 2 1 1 4 1 1 8 1 7 8 1 0 0 0 6 8 151
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Mixed-Signal-Electronics PD Dr.-Ing
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Stephan’s ambition for this cours
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Administratives Lecture: Stephan He
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The Macroscopic World is Purely Ana
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Topics of MSE Course Structure of
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Recommended Literature Analog Integ
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Constraints of Mixed Signal Circuit
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Generic Structure of Mixed-Signal S
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Representation of Discrete Time Sig
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Inverse Z-Transformation Methods f
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Representation of Discrete Time Sig
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low-pass low-pass low-pass Aliasing
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amplitude fsampling = 1 f signal,2
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Anti Aliasing Filter No brick wall
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Practical Sampling: Sample & Hold
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Xsh(!) = ¡ 1 j!¿ Sampling with Fi
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generalization X(s) = Relation Betw
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Downsampling II Mathematically dow
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Upsampling Stephan Henzler Mixed-Si
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Fractional Sample Rate Conversion
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Example for Simple Anti Aliasing Fi
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Transistor Description (for hand ca
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Chapter 2 Sample and Hold Circuits
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Sample & Hold Circuit Stephan Henzl
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Sample & Hold: Clock Feed-Through 3
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5. 6. Clock jitter Sample & Hold Ci
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Impact of Jitter on S&H Performance
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Noise due to jitter: Jitter Effect
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S&H with Correlated Double Sampling
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Noise of Sampled Signals: kT/C-Nois
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Closed Loop Track & Hold Circuit 1
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Closed Loop Track & Hold Circuit 3
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Summary Sample & Hold Circuits Step
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Resistor Realizations in MOS Techno
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Resistor Realizations in MOS Techno
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Switched Capacitor Resistor Emulati
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Resistor Equivalents Stephan Henzle
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Parameter Variations in SC Circuits
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Implementation of Integrated Capaci
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Vertical Parallel Plate Capacitor S
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Limitations of SC-Equivalence Steph
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Limitations of SC-Equivalence Switc
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Switched Capacitor Integrators Step
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z-Transformation Approximation on
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Analysis of Switched-Capacitor Circ
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Impact of Parasitic Capacitances C
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Switched Capacitor Amplifier Stepha
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SC Amplifier: Output Signal Stephan
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Superposition Theorem in SC Circuit
Page 99 and 100: Ideal Digital-to-Analog Conversion
Page 101 and 102: DAC Gain Error Stephan Henzler Mixe
Page 103 and 104: Ideal Analog-to-Digital Conversion
Page 105 and 106: Quantization in A/D-Converters Step
Page 107 and 108: Quantization in A/D-Converters Sig
Page 109 and 110: ADC Gain Error Stephan Henzler Mixe
Page 111 and 112: Non-Linearity in Data Converters St
Page 113 and 114: Nonlinearity in Data-Converters Ste
Page 115 and 116: DAC Nonlinearity: Differential Nonl
Page 117 and 118: ADC Nonlinearity: Integral Nonlinea
Page 119 and 120: Dynamic ADC Measurement ADC conver
Page 121 and 122: Harmonic Distortion Caused by Nonli
Page 123 and 124: Effective Number of Bits An ideal
Page 125 and 126: Other Useful Figures in Mixed-Signa
Page 127 and 128: Non-Linearity Gain Compression Co
Page 129 and 130: Superposition of Two Frequencies St
Page 131 and 132: Non-Linearity Cross Modulation Co
Page 133 and 134: Non-Linearity Intermodulation Two
Page 135 and 136: Non-Linearity: Further Reading Rec
Page 137 and 138: Chapter 5 Nyquist Rate Digital-to-A
Page 139 and 140: max value bus voltage follower stri
Page 141 and 142: Elmore Delay (cont.): Path Resistan
Page 143 and 144: Elmore Delay (cont): Delay Approxim
Page 145 and 146: Stephan Henzler Mixed-Signal-Electr
Page 147 and 148: Normalized Delay 300 250 200 150 10
Page 149: Stephan Henzler Mixed-Signal-Electr
Page 153 and 154: Implementation of Binary Weighted D
Page 155 and 156: High number of bits - large area Hi
Page 159 and 160: R-2R-Ladder Network Stephan Henzler
Page 163 and 164: SC-Amplifier with Controllable Capa
Page 165 and 166: Thermometer Code Converters (method
Page 167 and 168: Hybrid Converter Architectures Step
Page 169 and 170: Charge Scaling DAC Compatibel with
Page 171 and 172: Analog-to-Digital Converter Familie
Page 173 and 174: Dual-Slope Analog-to-Digital Conver
Page 175 and 176: Iterative Analog-to-Digital Convert
Page 177 and 178: Converter with Successive Approxima
Page 179 and 180: Converter with Successive Approxima
Page 181 and 182: Modified SAR Algorithm Stephan Henz
Page 183 and 184: Charge Redistribution SAR Converter
Page 185 and 186: Charge Redistribution SAR Converter
Page 187 and 188: Hybrid SAR Converters Search can b
Page 189 and 190: Detailed SAR Architecture Let’s
Page 191 and 192: Binary Weighted SAR Stephan Henzler
Page 193 and 194: Algorithmic Analog-to-Digital Conve
Page 197 and 198: Illustration in Robertson Diagram 2
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Voltage Doubling in Algorithmic Con
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Voltage Doubling in Algorithmic Con
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Pipelined ADC 1 Going for pipeline
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High-Speed ADC: Pipeline Processing
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Impact of Comparator Offset on ADC
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Impairments in SAR Algorithms Find
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Redundant SAR Algorithms Stage qua
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Subranging Principle quantization e
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Linear Model of Subranging ADC Step
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Linear Model of Subranging ADC Eff
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General Pipeline SAR ADC Stephan He
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Background Calibration for Stage Ga
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Summary Pipeline ADC Stage errors
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implemented as parallel connection
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thermometer code one-hot code trans
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Bubble Correction in Flash Converte
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Interpolating Flash Converter Steph
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Kickback Effect Especially in flas
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Folding ADC: Operation Principle St
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High-Speed ADC: Parallel Processing
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Chapter 7 Comparators Stephan Henzl
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Static Characteristics of Comparato
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Operational Amplifier as Comparator
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Comparator Propagation Delay Linea
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Track & Latch Circuit I Stephan Hen
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Principle of Track-and-Latch Stage
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Latched Comparators I Standard arc
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Track & latch circuit: Latched Comp
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Current Mode (CML) Latch Combines
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Elimination of Memory Effect Prech
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Chapter 8 Oversampled Converters Si
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Linear Model of Quantization Noise
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Quantization Noise and Oversampling
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Feasibility of Oversampling Goal:
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First Order Noise Shaping Stephan H
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First Order Noise Shaping Stephan H
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Calculation of Signal-to-Noise Rati
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SC Implementation of 1. Order ΣΔ
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Comparison Nyquist Rate vs. SD AD N
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Calculation of Transfer Functions S
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Simulation with Matlab/Simulink Ste
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Output Spectrum of ΣΔ-Modulator f
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Input Level Dependent SNR 2. Order
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Tones Stephan Henzler Mixed-Signal-
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Dithering Reduce the risk of tones
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maximum noise peak Tones input DC l
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STF of 3. Order ΣΔ-Modulator Step
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Cascaded ΣΔ-Modulator (Multi stAg
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3. Order MASH Structure Stephan Hen
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hist(S1) 12000 10000 8000 6000 4000
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hist(S1) 2.5 2 1.5 1 0.5 0 -1 -0.8
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ΣΔ-Analog-to-Digital Conversion S
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Sinc-Filter Basic low-pass filter a
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Sinc Filter Transfer Functions Step
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Implementation of Sinc-Filter Steph
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ΣΔ-Digital-to-Analog Conversion S
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Continuous Time Sigma-Delta Convert
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Comparison of Discrete- and Continu
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Web References Murmann. VLSI Data
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