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Mixed-Signal-Electronics<br />
PD Dr.-Ing. Stephan Henzler<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
1
henzler@tum.de<br />
Lecturer CV<br />
Stephan Henzler received the Dipl.-Ing. degree in<br />
electrical engineering in 2002, the Dr.-Ing. degree in 2006,<br />
and the habilitation 1 degree in 2010 from the Technische<br />
Universität München (<strong>TUM</strong>), Germany. From 2002 to<br />
2005, he was with the Institute for Technical Electronics,<br />
Technische Universität München, where he worked on<br />
low-power digital integrated circuit design and leakage<br />
reduction techniques. For his dissertation on power<br />
management and leakage reduction techniques he<br />
received the Rhode-und-Schwarz outstanding thesis<br />
award 2007. In 2005, he joined the Advanced Systems<br />
and Circuits Department of Infineon Technologies AG,<br />
Munich, where he worked on high-speed/highperformance<br />
digital integrated circuits, variability in deepsubmicron<br />
CMOS technologies, and mixed-signal circuit<br />
design in nanometer CMOS technologies, especially timeto-digital<br />
converters. In 2010 he joined the wireless mixedsignal<br />
department of Infineon where he works on mixedsignal<br />
system and circuit design. Since February 2011 he<br />
carries on the same responsibilities within Intel.<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
2
Stephan’s ambition for this course …<br />
Simplicity is the Ultimate Sophistication<br />
Leonardo Da Vinci<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
But don’t misunderstand,<br />
this does not mean that you<br />
don’t have to exercise!<br />
3
Course and Online Material<br />
Lecture notes<br />
available in the Fachschaft EI (<strong>TUM</strong>), handout (GIST <strong>TUM</strong> Asia)<br />
Online material comprising<br />
– annotated slides<br />
– video stream of last years lectures (GIST <strong>TUM</strong> Asia)<br />
www.lte.ei.tum.de/homes/henzler<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
4
Administratives<br />
Lecture: Stephan Henzler<br />
henzler@tum.de<br />
office hours: during lecture time<br />
Tutorial: Nasim Pour Aryan<br />
n.aryan@tum.de<br />
office hours: during tutorial time<br />
Exam: in written form,<br />
Credits: 4.5 ECTS credits (<strong>TUM</strong>)<br />
Language: english<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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The Macroscopic World is Purely Analog<br />
motion/acceleration<br />
mechanical force<br />
sound waves<br />
light<br />
electromagnetic<br />
field<br />
temperature<br />
Digital System, e.g.<br />
- digital communication<br />
(DSL, GSM, …, LTE)<br />
- computer equipment<br />
- multimedia<br />
(DVD, mp3, camera… )<br />
- control application<br />
(e.g. automotive)<br />
discrete sequence of<br />
numbers from a discrete set<br />
continuous time<br />
Our environment is always analog … and values<br />
You just have to investigate the system in-depth!<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
sense organs<br />
sensors/<br />
actuators<br />
time<br />
even ‘digital’<br />
signals on a<br />
transmission<br />
channel<br />
6
The Macroscopic World is Purely Analog<br />
motion/acceleration<br />
mechanical force<br />
sound waves<br />
light<br />
electromagnetic<br />
field<br />
ADC<br />
DAC<br />
Digital System, e.g.<br />
- digital communication<br />
(DSL, GSM, …, LTE)<br />
- computer equipment<br />
- multimedia<br />
(DVD, mp3, camera… )<br />
- control application<br />
(e.g. automotive)<br />
discrete sequence of<br />
numbers from a discrete set<br />
The mixed-signal shell is a bridge between<br />
temperature sense organs<br />
– the analog environment and the digital signal processing<br />
– the physical representation (voltage/current) and a mathematical abstraction<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
sensors/<br />
actuators<br />
time<br />
even ‘digital’<br />
signals on a<br />
transmission<br />
channel<br />
7
Generic Mixed Signal System<br />
What means mixed-signal?<br />
Mixed-signal refers to a system which processes both analog<br />
and digital signals and which contains converter blocks that<br />
enable interaction between the two domains.<br />
Often related to SOC (System-on-Chip)<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Topics of MSE Course<br />
Structure of mixed signal systems and mathematical<br />
representation of discrete time signals.<br />
ADC<br />
discrete time<br />
discrete states<br />
discrete time (step function)<br />
continuous states<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
digital discrete time (step function)<br />
discrete values (states)<br />
9
Sample & hold circuits<br />
Topics of MSE Course<br />
Switched-capacitor circuits<br />
Data converter fundamentals (ADC, DAC)<br />
converter parameters and characteristics<br />
Nyquist rate D/A Converters<br />
Nyquist rate A/D Converters<br />
Oversampling Converters: Sigma Delta Converters<br />
Outlook: More mixed signal building blocks<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Recommended Literature<br />
Analog Integrated Circuit Design.<br />
David A. Johns<br />
Ken Martin<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
Relevant chapters:<br />
Chapter 7:<br />
Comparators.<br />
Chapter 8:<br />
Sample-and-Holds<br />
Chapter 9:<br />
Discrete Time Signals<br />
Chapter 10:<br />
Switched Capacitor Circuits<br />
Chapter 11:<br />
Data Converter Fundamentals<br />
Chapter 12:<br />
Nyquist-Rate D/A Converters<br />
Chapter 13:<br />
Nyquist-Rate A/D Converters<br />
Chapter 14:<br />
Oversampling Converters<br />
11
Additional Literature & References<br />
Razavi. Principles of Data Conversion System Design.<br />
Wiley, 1994.<br />
Allen, Holberg. CMOS Analog Circuit Design. Oxford, 2010.<br />
Baker, Li, Boyce. CMOS Circuit Desig, Layout, Simulation.<br />
Wiley, 1997.<br />
Gregorian, Temes. Analog MOS Integrated Circuits for<br />
Signal Processing. Wiley 1986.<br />
Oppenheim. Time Discrete Signal Processing. Oldenbourg<br />
Norsworthy, Schreier, Temes. Delta-Sigma Data<br />
Converters. IEEE Press, 1997.<br />
Schreier, Temes. Understanding Delta Sigma Data<br />
Converters. IEEE Press 2005.<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Constraints of Mixed Signal Circuits in SoC<br />
PROS CONS<br />
• Cheap implementation of complex<br />
signal processing tasks<br />
• System-on-chip (SOC)<br />
Small pcb footprint<br />
• Fast time reference/clock<br />
• Digitally assisted analog<br />
• All advantages of digital<br />
systems, e.g. robustness, noise<br />
immunity, data storage,<br />
reconfigurability, efficient highly<br />
automated design and test<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
• Need to build analog circuits in<br />
digital process, i.e.<br />
• Devices optimized for high<br />
switching speed not for analog,<br />
(e.g. small gm/gds)<br />
• Transistors with high field<br />
and short channel effects<br />
µ(V G), V th(W,L,V DS,V BS), I gate, I DB<br />
• Signal contamination due to digital<br />
switching noise, e.g. cross talk,<br />
supply noise substrate coupling<br />
• several 100mA digital currents<br />
• V analog signals<br />
13
Chapter 1<br />
Basics of Mixed-Signal Electronics<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Generic Structure of Mixed-Signal Systems<br />
System Perspective<br />
Circuit Perspective<br />
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Representation of Discrete Time Signals and<br />
Spectral Transformation<br />
xs(t) = xc(t) X<br />
= X<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
n<br />
n<br />
±(t ¡ nT )<br />
x(nT )±(t ¡ nT )<br />
= X<br />
x[n]±(t ¡ nT )<br />
n<br />
16
Representation of Discrete Time Signals and<br />
Spectral Transformation<br />
Fourier Transformation<br />
X(!) =<br />
generalization<br />
s = j<br />
+1<br />
Z<br />
¡1<br />
x(t) = 1<br />
2¼<br />
x(t)e ¡j!t dt<br />
+1<br />
Z<br />
¡1<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
X(!)e j!t d!<br />
X(s) =<br />
+1<br />
Z<br />
¡1<br />
x(t)e ¡st dt<br />
Laplace Transformation<br />
17
Spectral Transformation of Discrete Time Signal<br />
Insertion of sampled signal in Fourier formula:<br />
X(!) =<br />
+1 Z<br />
X<br />
¡1<br />
= X<br />
Normalization of frequency to sampling frequency:<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
n<br />
n<br />
x(nT )<br />
x(nT )±(t ¡ nT )e ¡j!t dt<br />
+1<br />
Z<br />
¡1<br />
= X<br />
x(nT )e ¡j!nT<br />
n<br />
e ¡j!t ±(t ¡ nT )dt<br />
X() = X<br />
x[n]e ¡jn X(z) = X<br />
x[n]z ¡n<br />
n<br />
FT of discrete sequence<br />
generalization<br />
z = e j = e j!T<br />
FT of sampled signal<br />
= !T = 2¼f<br />
n<br />
z-Transformation<br />
fs<br />
18
Inverse Z-Transformation<br />
Methods for computation of inverse z-transformation<br />
– Tabular method<br />
– Decomposition in partial fractions and tabular method<br />
– Power series method<br />
(coefficients correspond to time sequence)<br />
Formal inversion:<br />
x[n] = 1<br />
2¼<br />
I<br />
c X(z)zn¡1 dz<br />
= X residues of X(z)z n¡1 at poles within C<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Representation of Discrete Time Signals and<br />
Spectral Transformation<br />
Meaning of frequency: oscillations per second.<br />
What is meaning of normalized frequency Ω?<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
Ω = angular change from sample to sample<br />
20
Representation of Discrete Time Signals and<br />
Spectral Transformation<br />
Spectrum of a sampled signal:<br />
s(t) = X<br />
±(t ¡ nT ) $ S(!) = 2¼<br />
T<br />
n<br />
xs(t) = xc(t) ¢ s(t) $<br />
Sampling means multiplication<br />
of continuous time signal with<br />
pulse train<br />
X<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
k<br />
±(! ¡ k!s) !s = 2¼<br />
T<br />
Xs(!) = 1<br />
2¼ Xc(!) ¤ S(!)<br />
= 1<br />
T Xc(!) ¤ X<br />
= 1<br />
T<br />
X<br />
k<br />
In frequency domain this translates<br />
into convolution of signal spectrum<br />
with spectrum of pulse train.<br />
This is simply a copy and shift of<br />
the spectrum to multiples of the<br />
sampling frequency<br />
k<br />
Xc(! ¡ k!s)<br />
±(! ¡ k!s)<br />
21
Representation of Discrete Time Signals and<br />
Spectral Transformation<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
Aliasing occurs if mirror spectra overlap<br />
22
low-pass<br />
low-pass<br />
low-pass<br />
Aliasing in the Frequency Domain<br />
low-pass filtering<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
t<br />
t<br />
t<br />
theoretical case as brick wall<br />
filter would be required<br />
t<br />
t<br />
t<br />
23
amplitude fsampling = 1 f signal,1 = 0.22<br />
1<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
0<br />
-0.2<br />
-0.4<br />
-0.6<br />
-0.8<br />
-1<br />
Sampling and Aliasing 1<br />
0 5 10 15<br />
samples<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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amplitude fsampling = 1 f signal,2 = 0.22 + fsampling<br />
1<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
0<br />
-0.2<br />
-0.4<br />
-0.6<br />
-0.8<br />
-1<br />
Sampling and Aliasing 2<br />
0 5 10 15<br />
samples<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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amplitude<br />
1<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
0<br />
-0.2<br />
-0.4<br />
-0.6<br />
-0.8<br />
-1<br />
Sampling and Aliasing 3<br />
Only with the Nyquist criterion it is assured that the samples<br />
represent the signal unambiguously<br />
0 5 10 15<br />
samples<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Anti Aliasing Filter<br />
No brick wall filter with infinitely steep transition band<br />
Real filters have a transition band<br />
– Nyquist rate is a theoretical limit but not feasible<br />
– Tradeoff between sample rate and filter order<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Practical Sampling: Sample & Hold<br />
Remember: All realizable signals have<br />
– finite slope (dx/dt)<br />
– finite pulse width, i.e. finite bandwidth<br />
– finite value<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
t<br />
t<br />
t<br />
ideal sampling<br />
step function<br />
alternative solution<br />
28
Practical Sampling: Sample & Hold<br />
Remember: All realizable signals have<br />
– finite slope<br />
– finite pulse width<br />
– finite bandwidth<br />
– finite value<br />
Hence sampling means always SAMPLE & HOLD<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Sampling with Finite Pulse Width<br />
x sh(t) = xs(t) ¤ h(t)<br />
=<br />
x sh(!) = 1<br />
¿<br />
= 1<br />
¿<br />
1X<br />
n=¡1<br />
+1<br />
Z<br />
¡1<br />
1X<br />
= ¡ 1<br />
j!¿<br />
xc[n] 1<br />
¿ [¾(t ¡ nT ) ¡ ¾(t ¡ nT ¡ ¿)]<br />
1X<br />
n=¡1<br />
n=¡1<br />
1X<br />
xc[n]<br />
n=¡1<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
xc[n] [¾(t ¡ nT ) ¡ ¾(t ¡ nT ¡ ¿)] e ¡j!t dt<br />
nT +¿<br />
Z<br />
nT<br />
e ¡j!t dt<br />
xc[n] h<br />
e ¡j!ti nT +¿<br />
nT<br />
(t)<br />
t<br />
30
Xsh(!) = ¡ 1<br />
j!¿<br />
Sampling with Finite Pulse Width<br />
=<br />
1X<br />
n=¡1<br />
Distortion of base band and damping of mirror spectra<br />
– visible in DAC<br />
– not visible in ADC<br />
1X<br />
n=¡1<br />
xc[n]e ¡j!nT<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
xc[n] ³<br />
e ¡j!nT e ¡j!¿ ´<br />
¡ e<br />
¡j!nT<br />
1<br />
j!¿<br />
= Xs(!)e ¡1 2j!¿ ej 1 2 !¿ ¡ e ¡j 1 2 !¿<br />
2j 1 2 !¿<br />
= Xs(!)e ¡j 1 2 !¿ sin ³ 1<br />
2 !¿ ´<br />
³<br />
´<br />
1 ¡ e<br />
¡j!¿<br />
ideal sampling X S() impact of hold<br />
1<br />
2 !¿<br />
31
Representation of Discrete Time Signals and<br />
Spectral Transformation<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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generalization<br />
X(s) =<br />
Relation Between s- and z-Plain<br />
Fourier Transformation:<br />
+1 Z<br />
X(!) =<br />
¡1<br />
x(t)e ¡j!t dt<br />
LaPlace Transformation: z-Transformation:<br />
+1 Z<br />
1X<br />
j<br />
¡1<br />
x(t)e ¡st dt X(z) =<br />
s<br />
<br />
z = e j!T<br />
discrete<br />
signals<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
Im(z)<br />
1X<br />
n=¡1<br />
x(nT )e ¡j!nT<br />
normalization<br />
&<br />
generalization<br />
n=¡1<br />
z<br />
x[n]z ¡n<br />
Re(z)<br />
33
Downsampling<br />
Intuitive view:<br />
If the analog signal was sampled directly with the low rate we<br />
would get every 1 out of L samples<br />
remove all other samples, keep only 1 out of L<br />
Additional information: If there is noise between the repeated signal spectra, or if the Nyquist criterion cannot be guaranteed for the<br />
down-sampled signal an additional filtering is required (low pass). However, it is sufficient to compute one out of L samples.<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Downsampling II<br />
Mathematically downsampling comprises two steps:<br />
– digital sampling, i.e. multiplication with a periodic<br />
1,0,0, …, 0, 1, 0, … sequence<br />
– dropping of all zero weighted samples and scaling of<br />
frequency axis<br />
In spectrum this means a copy and shift of the already<br />
periodic signal<br />
risk of aliasing<br />
eventually AAF prior to downsampling (decimation filter)<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
Spectrum of sampling fcunction:<br />
35
decimation filter<br />
Downsampling III<br />
Down-sampling requires, that there is no signal energy in<br />
between baseband and mirror spectra (e.g. noise)<br />
In general this is not the case, so down-sampling may cause<br />
aliasing<br />
To avoid aliasing a low pass filter is required in front of downsampling<br />
block Decimation Filter (Decimator)<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Upsampling<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
imaging<br />
Additional information: Fractional sample rate conversion is up-sampling combined with down-sampling. Low-pass filters<br />
may be shared. Compute only what is necessary!<br />
37
Upsampling II<br />
Zero padding results in higher sampling rate<br />
However, this does not mean that mirror spectra occur only<br />
at multiples of the sampling frequency<br />
Imaging, i.e. replica in between 0..2<br />
Low pass filter removes images<br />
– Result in frequency domain: Replica only at k x f s<br />
– Result in time domain: Zeros move on real signal curve<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
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Fractional Sample Rate Conversion<br />
Purpose: Change sample rate by a non-integer factor L/M<br />
Two possibilities:<br />
– Up-sampling by L, down-sampling by M<br />
– Down-sampling by M, than up-sampling by L<br />
The order of up- and down-sampling may be exchanged<br />
without any change in the input/output behavior if the<br />
decimation factor M and the interpolation factor L are<br />
relatively prime.<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
39
Components of a Mixed Signal System<br />
Structure of mixed signal systems and mathematical<br />
representation of discrete time signals.<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
40
Example for Simple Anti Aliasing Filter<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
41
Supply Voltages of Mixed Signal Circuits<br />
General case: use of bipolar signals<br />
VDD<br />
AGND<br />
VSS<br />
most positive potential<br />
positive signals<br />
analog ground / reference voltage<br />
(reference point for analog signals)<br />
negative signals<br />
most negative potential<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
+2V<br />
Even more complex supply concepts in use check for available voltages and definitions before starting with design<br />
0V<br />
-2V<br />
4V<br />
2V<br />
0V<br />
42
Transistor Description (for hand calculations)<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
43
Condutance G<br />
V SS<br />
MOS Transistor as Switch<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
V DD<br />
44
Chapter 2<br />
Sample and Hold Circuits<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
45
Practical Sampling: Sample & Hold<br />
Remember: All realizable signals have<br />
– finite slope<br />
– finite pulse width<br />
– finite value<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
t<br />
t<br />
t<br />
46
Sample & Hold Circuit<br />
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47
Sample & Hold Circuit (cont)<br />
1. Finite rise-time / finite bandwidth due to RC constant<br />
2. Amplifier dynamics<br />
(finite settling time, overshoot, ringing)<br />
Driving amplifier sees a varying load impedance<br />
(RC input isolation can reduce effect)<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
48
Sample & Hold: Clock Feed-Through<br />
3. Clock feed-through due to capacitive coupling.<br />
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49
Sample & Hold: Charge Injection<br />
4. Charge Injection: mobile carriers are removed<br />
1:1 distribution is a approximation for fast switching<br />
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50
5.<br />
6. Clock jitter<br />
Sample & Hold Circuit (cont)<br />
7. Droop in hold mode: leakage currents discharge hold cap<br />
8. Linearity<br />
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S&H Output Signal<br />
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52
Impact of Jitter on S&H Performance<br />
Consider a sinusoidal signal<br />
Signal power<br />
Rate of change<br />
Jitter = random variation of sampling instance<br />
Sampling error:<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
53
Impact of Jitter on S&H Performance<br />
Noise power resulting from sampling error<br />
Signal-to-Noise Ratio<br />
maximum achievable SNR for given jitter<br />
frequency dependent, i.e. the larger the bandwidth the higher<br />
the clock requirements<br />
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Noise due to jitter:<br />
Jitter Effect Analysis<br />
A noise floor which scales with signal frequency and<br />
amplitude is an indication for dominant aperture and jitter<br />
effects.<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
55
Impact of Offset-Voltage<br />
Offset voltage of opamp is modeled as voltage source in<br />
series to input terminal<br />
V o<br />
Offset voltage is directly visible at output terminal<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
56
S&H with Correlated Double Sampling<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
57
Noise in Discrete Time Systems<br />
Noise is a random process statistical description is required<br />
time domain: noise signal a(t)<br />
frequency domain: power spectral density<br />
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58
Noise of Sampled Signals: kT/C-Noise<br />
White noise with power spectral density is<br />
low-pass filtered:<br />
Noise power:<br />
independent on R<br />
Remarks:<br />
• Sampling makes this a little bit more complicated as noise is a wide band signal so there is aliasing of replica<br />
spectra. However, the noise power in the baseband is still kT/C<br />
• This is only a lower bound of noise power, buffers contribute also to overall noise power<br />
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59
Assumption:<br />
–<br />
–<br />
Noise Reduction Techniques<br />
Average over 4 samples<br />
Generally:<br />
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60
Closed Loop Track & Hold Circuit 1<br />
Basic sampling circuit is embedded in feedback loop<br />
– Very high input impedance<br />
– Reduction of non-idealities (e.g. buffer offset) by loop gain<br />
– Loop must be designed stable speed degradation<br />
– Feedback is broken during hold mode<br />
• Input opamp saturates<br />
offset not canceled<br />
• Long slewing time when circuit returns to track mode<br />
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not critical wrt. offset errors<br />
61
Closed Loop Track & Hold Circuit 2<br />
Hold mode:<br />
Input opamp is configured as voltage follower<br />
fast settling when circuit returns to track mode<br />
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62
Closed Loop Track & Hold Circuit 3<br />
Storage capacitor is shifted to feedback loop of output<br />
amplifier (integrator)<br />
Swing across switch is always near to AGND<br />
Error injection becomes nearly signal independent (pedestal error)<br />
No appertur jitter<br />
Input opamp is grounded during hold phase<br />
fast settling when switched to track mode<br />
signal feedthrough is minimized<br />
Reduced speed due to stability requirements<br />
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63
Closed Loop Track & Hold Circuit 4<br />
Additional error replica to avoid the pedestal error<br />
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64
Summary Sample & Hold Circuits<br />
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65
Chapter 3<br />
Switched Capacitor Circuits<br />
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66
Resistor Realizations in MOS Technologies: Poly-Resistor<br />
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Sheet resistance:<br />
200-400Ω□<br />
(metal
Resistor Realizations in MOS Technologies: Diffusion Resistor<br />
Sheet resistance: 50-150Ω□<br />
Highly variable resistance (up to +/- 20%)<br />
Parasitic diode<br />
High parasitic capacitances<br />
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68
Resistor Realizations in MOS Technologies<br />
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L<br />
R <br />
R[]<br />
Wd<br />
Sheet resistance:<br />
Poly: 200-400Ω□<br />
Diffusion: 50 -150Ω□<br />
Metal:
Effect of Resistor between two Nodes<br />
continuous time point-of-view discrete time point-of-view<br />
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70
Switched Capacitor Resistor Emulation 1<br />
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71
Switched Capacitor Resistor Emulation 2<br />
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72
Resistor Equivalents<br />
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73
Non-Overlapping Multiphase Clocking<br />
both clocks active at the same time<br />
would cause short circuit currents<br />
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74
Parameter Variations in SC Circuits 1<br />
What is the variation of a RC time constant?<br />
i.e. the relative error of the time constant is equal to the sum of<br />
the relative error of the resistance and the capacitance<br />
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75
Parameter Variations in SC Circuits 2<br />
What happens for the switched-capacitor equivalent?<br />
i.e. the relative error of the time constant is equal to the relative<br />
error of a capacitance ratio<br />
very small if matching is considered in layout<br />
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76
Implementation of Integrated Capacitors<br />
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77
Alternative Capacitor Implementation<br />
Junction capacitance<br />
– Parasitic diode leakage<br />
– Voltage and temperature dependent<br />
MOS capacitance<br />
– MOS transistor in accumulation or inversion<br />
– Alternatively: gate over diffusion<br />
– Strongly non-linear<br />
– Very high capacitance/area<br />
– God for decoupling<br />
Vertical parallel plate capacitor<br />
– Matrix of wires exploiting vertical and lateral capacitance<br />
– Ref. next slide<br />
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78
Vertical Parallel Plate Capacitor<br />
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Kim, VLSI Symposium 2003<br />
79
Limitations of SC-Equivalence<br />
Continuous Time RC-Low-Pass<br />
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80
Limitations of SC-Equivalence<br />
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S 1 and S 2 are<br />
closed alternately<br />
81
Limitations of SC-Equivalence<br />
Switched Capacitor Low-Pass<br />
z-Transformation:<br />
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82
Limitations of SC-Equivalence<br />
Switched Capacitor Equivalence<br />
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83
Switched Capacitor Integrators<br />
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84
Switched Capacitor Integrators<br />
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85
Analysis of Switched-Capacitor Circuits<br />
– SC-Cookbook –<br />
Mark polarity of all capacitors (arbitrarily)<br />
Do not change this polarity during the analysis<br />
Draw equivalent circuit for each clock phase<br />
Charge balance analysis for full cycle<br />
– assume steady state conditions for each time step<br />
– compute ∆Q that occurs during phase transitions<br />
z-transformation<br />
Calculate transfer function<br />
Evaluate transfer function on unit circle of z-plane<br />
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86
z-Transformation<br />
Approximation on unit circle<br />
Spectral Analysis<br />
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87
Spectral Analysis (cont.)<br />
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88
Analysis of Switched-Capacitor Circuits<br />
– SC-Cookbook –<br />
Mark polarity of all capacitors (arbitrarily)<br />
Do not change this polarity during the analysis<br />
Draw equivalent circuit for each clock phase<br />
Charge balance analysis for full cycle<br />
– assume steady state conditions for each time step<br />
– compute ∆Q that occurs during phase transitions<br />
z-transformation<br />
Calculate transfer function<br />
Evaluate transfer function on unit circle of z-plane<br />
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89
Time Domain Behavior<br />
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90
Impact of Parasitic Capacitances<br />
C p1||C 1 direct impact on transfer behavior <br />
C p2 shorted no impact <br />
C p3 shorted between GND and VGND <br />
C p4 at opamp output negligible impact <br />
H<br />
C<br />
1 p1<br />
z <br />
1<br />
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C<br />
C<br />
2<br />
z<br />
1<br />
z<br />
1<br />
91
Alternative Integrator Architectures<br />
Sign of transfer function can be changed by switching the<br />
control signal of the switches.<br />
Less sensitive to parasitic capacitances<br />
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92
Switched Capacitor Amplifier<br />
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93
Switched Capacitor Amplifier: Impact of Offset<br />
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94
SC Amplifier: Output Signal<br />
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opamp offset<br />
95
Switched Capacitor Amplifier<br />
(without output reset)<br />
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96
Superposition Theorem in SC Circuits<br />
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97
Chapter 4<br />
Data Converter Fundamentals<br />
"He who loves practice without theory is like the<br />
sailor who boards ship without a rudder and<br />
compass and never knows where he may cast“<br />
Leonardo Davinci<br />
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98
Ideal Digital-to-Analog Conversion<br />
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99
DAC Offset Error<br />
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100
DAC Gain Error<br />
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101
Digital-to-Analog Converter Model<br />
ideal model 1 st order model<br />
Gain of ideal converter depends on interpretation of DAC<br />
input bits. <strong>Here</strong>, a fractional interpretation is used.<br />
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102
Ideal Analog-to-Digital Conversion<br />
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103
Analog-to-Digital Converter Model I<br />
Depending on implementation quantization block can be<br />
– round function<br />
– floor function<br />
– ceil function<br />
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104
Quantization in A/D-Converters<br />
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105
Quantization in A/D-Converters<br />
Consider one saw tooth, e.g.<br />
Mean quantization error:<br />
Power of quantization error:<br />
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106
Quantization in A/D-Converters<br />
Signal-to-(Quantization)-Noise Ratio S(Q)NR:<br />
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107
ADC Offset Error<br />
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108
ADC Gain Error<br />
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109
Analog-to-Digital Converter Model II<br />
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110
Non-Linearity in Data Converters<br />
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111
Example of Non-Linear Transfer Characteristic<br />
x<br />
non-linear<br />
system<br />
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y<br />
112
Nonlinearity in Data-Converters<br />
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Accuracy:<br />
The absolute inaccuracy is<br />
defined as the maximum<br />
deviation of the actual analog<br />
value from the ideal one. It<br />
includes offset, gain and<br />
linearity errors and may be<br />
different for every individual<br />
quantization value.<br />
The relative inaccuracy is<br />
defined as the deviation that<br />
remains after offset and gain<br />
error have been removed.<br />
113
DAC Nonlinearity: Integral Nonlinearity<br />
Integral Nonlinearity (INL) Error:<br />
The INL error is defined as the deviation of each analog value from a straight<br />
line. If the straight line through the endpoints of the converter’s transfer curve<br />
is chosen (left) as reference, the INL equals the relative inaccuracy.<br />
Alternatively a regression line can be used as reference (right). It depends on<br />
the application which definition should be applied.<br />
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114
DAC Nonlinearity: Differential Nonlinearity<br />
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Differential Nonlinearity (DNL):<br />
Deviation of the analog step size<br />
from 1VLSB (after removal of gain<br />
and offset error). Like the INL the<br />
DNL value is defined individually<br />
for each digital word<br />
Monotonicity:<br />
The output signal of a monotonic<br />
D/A converter increases or<br />
remains at least unchanged as<br />
the input signal increases.<br />
115
ADC Nonlinearity: Inaccuracy<br />
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Accuracy:<br />
The absolute inaccuracy is<br />
defined as the maximum<br />
deviation of the actual analog<br />
value from the ideal one. It<br />
includes offset, gain and<br />
linearity errors and may be<br />
different for every individual<br />
quantization value.<br />
The relative inaccuracy is<br />
defined as the deviation that<br />
remains after offset and gain<br />
error have been removed.<br />
116
ADC Nonlinearity: Integral Nonlinearity<br />
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Integral Nonlinearity (INL):<br />
The INL error is defined as the<br />
deviation of each analog value<br />
from a straight line (after<br />
removal of gain and offset error).<br />
If the straight line through the<br />
endpoints of the converter’s<br />
transfer curve is chosen as<br />
reference, the INL equals the<br />
relative inaccuracy. Alternatively<br />
a regression line can be used as<br />
reference. It depends on the<br />
application which definition<br />
should be applied.<br />
117
ADC Nonlinearity: Differential Nonlinearity<br />
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Differential Nonlinearity (DNL):<br />
Deviation of the analog step size<br />
from 1VLSB (after removal of gain<br />
and offset error). Like the INL the<br />
DNL value is defined individually<br />
for each digital word<br />
Missing Codes:<br />
If one step vanishes completely<br />
the ADC is said to have a missing<br />
code. In practice the criterion for a<br />
missing code is a step width<br />
smaller than 0.1 x VLSB<br />
118
Dynamic ADC Measurement<br />
ADC converter characteristics<br />
describe static measurements<br />
In dynamic measurements a input<br />
voltage waveform (usually a sine signal)<br />
is converted continuously and<br />
analyzed in the frequency domain.<br />
(much more realistic, noise, crosstalk, etc.)<br />
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119
[FS]<br />
Interpretation of the Output spectrum<br />
noise floor<br />
test signal<br />
A sin(wt)<br />
harmonics<br />
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Robertson, ISSCC, 2002<br />
0.5 x<br />
sampling<br />
frequency<br />
120
Harmonic Distortion Caused by Nonlinearity<br />
Nonlinearity causes harmonic distortion<br />
Spectrum allows computation of<br />
– signal power<br />
– power of harmonic components<br />
– noise power<br />
Signal-to-Noise Ratio:<br />
<br />
SNR 10<br />
log<br />
<br />
10<br />
<br />
Signal-to-Noise-and-Distortion Ratio<br />
<br />
SNDR 10<br />
log<br />
<br />
10<br />
<br />
signal<br />
noise<br />
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P<br />
noise<br />
P<br />
P<br />
P<br />
<br />
signal<br />
P<br />
<br />
<br />
<br />
<br />
harmonics<br />
<br />
<br />
<br />
<br />
121
Harmonic Distortion Caused by Nonlinearity<br />
Total Harmonic Distortion (THD)<br />
THD<br />
<br />
20<br />
log10<br />
Second Harmonic Distortion (SHD)<br />
SHD<br />
V<br />
2<br />
V<br />
2<br />
V<br />
2<br />
<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
<br />
<br />
<br />
<br />
20<br />
2<br />
log10<br />
<br />
<br />
<br />
<br />
3<br />
V<br />
V<br />
V<br />
1<br />
2<br />
1<br />
<br />
<br />
<br />
<br />
4<br />
<br />
<br />
<br />
<br />
<br />
122
Effective Number of Bits<br />
An ideal ADC suffers only from quantization noise<br />
SNR <br />
SQNR 6. 02dB<br />
N 1.<br />
76dB<br />
Actual ADCs have lots of impairments (noise, nonlinearity)<br />
that limit the effective resolution.<br />
Effective number of Bits:<br />
ENOB<br />
SNDR<br />
6.<br />
02<br />
1.<br />
76<br />
dB<br />
Note: The number of bits coming out of an ADC doesn‘t say<br />
anything about the actual resolution<br />
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<br />
dB<br />
123
Signal-to-Noise Ratio over Input Signal<br />
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124
Other Useful Figures in Mixed-Signal<br />
Crest Factor = Peak-to-Average Ratio<br />
Measure for dynamics of a signal defined by the quotient of<br />
the peak amplitude and the RMS value<br />
C <br />
max<br />
x(<br />
t)<br />
<br />
2<br />
x ( t)<br />
ADC Figure-of-Merit:<br />
Measure for the efficiency of an ADC<br />
FOM<br />
power<br />
frequency 2<br />
ENOB<br />
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<br />
125
Why is Linearity so Important?<br />
Let‘s consider a basic example of third order non-linearity<br />
The following equalities are useful<br />
Harmonic Distortion:<br />
A single tone transforms into a dc offset and multiple tones at<br />
multiples of the original input frequency<br />
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x<br />
non-linear<br />
system<br />
y<br />
126
Non-Linearity Gain Compression<br />
Consider only the fundamental (i.e. for low amplitude)<br />
For small amplitude A the gain of the system is a 1<br />
With increasing amplitude A, the high order term becomes<br />
noticeable, i.e. the gain becomes<br />
For a compressive system<br />
(a 3
Superposition of two Frequencies<br />
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128
Superposition of Two Frequencies<br />
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129
Non-Linearity Desensitization<br />
Consider superposition of weak signal and a strong interferer<br />
Strong signal causes large excitation around operating point<br />
effective gain reduction<br />
Small signal gain may become even zero<br />
blocking<br />
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130
Non-Linearity Cross Modulation<br />
Consider again superposition of weak signal and a strong<br />
interferer, but now with modulation of interferer<br />
Amplitude variation m 2 may be either noise or modulation<br />
Signal in band around 1<br />
Modulation/noise of the carrier 2 is transferred 1<br />
Effect occurs if multiple channels are processed by same<br />
non-linear system, e.g. non-linear amplifier in wireless base<br />
station<br />
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131
Non-Linearity Intermodulation<br />
Harmonics can be used to quantify the non-linearity of mixedsignal<br />
system.<br />
If the system is frequency selective, e.g. a low-pass filter<br />
some or even all harmonics are damped<br />
system seems to be less non-linear than it actually is.<br />
Measure non-linearity in band of interest, i.e. without<br />
damping effects Intermodulation Experiment<br />
Two-Tone Test:<br />
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132
Non-Linearity Intermodulation<br />
Two tones passing a non-linear system result in<br />
– Harmonics of first frequency<br />
– Harmonics of second frequency<br />
– Intermodulation products (caused by mixing signals)<br />
If the frequency difference is small, i.e. 2 - 1
Non-Linearity Intermodulation<br />
Intermodulation distortion = 3 rd IM product / fundamental<br />
(Amplitude must be known for interpretation)<br />
Assume small amplitudes, i.e. the amplitude of the<br />
fundamental can be expressed by a 1A and the IM3 is 3/4a 3A 3<br />
Third order intercept point describes the amplitude where the<br />
IM3 equals the fundamental<br />
(Hypothetical as for high amplitudes higher order non-linearity becomes noticeable, i.e. meas. is done for small amplitudes followed by extrapolation)<br />
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134
Non-Linearity: Further Reading<br />
Recommended Literature:<br />
– Razavi. RF Microelectronics. Prentice Hall.<br />
– Robertson. Specification and Figures of Merit for<br />
Mixed-Signal Circuits. ISSCC Tutorial 2002.<br />
– Razavi. Principles of Data Conversion System Design.<br />
Wiley, 1994.<br />
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135
Binary Number Representation<br />
# #<br />
normalized<br />
Sign<br />
magnitude<br />
1‘s<br />
complement<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
2‘s<br />
complement<br />
Offset<br />
binary<br />
+7 +7/8 0111 0111 0111 1111<br />
+6 +6/8 0110 0110 0110 1110<br />
+5 +5/8 0101 0101 0101 1101<br />
+4 +4/8 0100 0100 0100 1100<br />
+3 +3/8 0011 0011 0011 1011<br />
+2 +2/8 0010 0010 0010 1010<br />
+1 +1/8 0001 0001 0001 1001<br />
+0 0 0000 0000 0000 1000<br />
-0 0 1000 1111<br />
-1 -1/8 1001 1110 1111 0111<br />
-2 -2/8 1010 1101 1110 0110<br />
-3 -3/8 1011 1100 1101 0101<br />
-4 -4/8 1100 1011 1100 0100<br />
-5 -5/8 1101 1010 1011 0011<br />
-6 -6/8 1110 1001 1010 0010<br />
-7 -7/8 1111 1000 1001 0001<br />
-8 -8/8 1000 0000<br />
136
Chapter 5<br />
Nyquist Rate<br />
Digital-to-Analog Converters<br />
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137
Nyquist Rate Digital-to-Analog Converters<br />
V<br />
out<br />
Basic Idea:<br />
• Generate all possible voltages which are possible<br />
according to eq. 1<br />
• Use switches to connect the voltage selected by B in to<br />
the output<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
ref<br />
in<br />
ref<br />
1<br />
2<br />
N<br />
b 2 b<br />
2 <br />
b <br />
V B V<br />
2<br />
1<br />
2<br />
N<br />
138
max value<br />
bus<br />
voltage follower<br />
strictly monotonic<br />
3-Bit Resistor String Converter<br />
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Generate all possible voltages with<br />
resistive voltage divider<br />
Switches = NMOS transistors<br />
Transmission gates enable<br />
– higher voltage range<br />
– but higher parasitic cap, area<br />
(layout more complicated)<br />
Buffer experiences high input<br />
voltage variation<br />
Slow due to buffer and analog mux<br />
How fast does the DAC settle<br />
139
Prerequisites:<br />
– one input only<br />
Elmore Delay<br />
– caps between network node and ground only<br />
– no resistive loops<br />
W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, 1948.<br />
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140
Elmore Delay (cont.): Path Resistance<br />
There is exactly one resistive path from a network node i to<br />
the input s.<br />
The sum of all resistances along this path is the path<br />
resistance R ii, e.g. R 44 = R 4 + R 3 + R 1<br />
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141
Elmore Delay: Shared Path Resistance<br />
The shared path resistance R ik is the sum of all resistances<br />
along the joint sub-path of the two paths s i and s k.<br />
Example: R i4 = R 1 + R 3<br />
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142
Elmore Delay (cont): Delay Approximation<br />
Elmore delay:<br />
First order approximation of the delay after which a voltage<br />
step at the input s can be observed at the output i.<br />
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SS 2008<br />
143
Elmore Delay (cont): Delay Approximation<br />
Elmore delay:<br />
Useful for<br />
– Estimation of wire delay<br />
– Estimation of DAC settling time<br />
– …<br />
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SS 2008<br />
144
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Resistor String Converter<br />
145
Resistor String Converter<br />
(with pass-gate decoder)<br />
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Normalized Delay<br />
300<br />
250<br />
200<br />
150<br />
100<br />
50<br />
Delay Comparison<br />
0<br />
0 2 4 6 8 10 12 14 16<br />
Number of Bits<br />
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string<br />
tree<br />
147
Folded Resistor String Converter<br />
Combine the advantages of both converters:<br />
(low effort for decoder, small load cap.)<br />
Access scheme as in memories:<br />
MSBs select row<br />
LSBs select column<br />
2<br />
N<br />
2<br />
transistors at output bus<br />
all bitlines are charged<br />
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148
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Multi-Stage<br />
Resistor String Converter<br />
Subdivde voltage range in<br />
coarse sub-intervals first<br />
Copy the respective voltage<br />
interval<br />
Fine interpolation of the<br />
copied interval<br />
• if opamps match the converter is monotonic<br />
• less resistors<br />
• reduced area and power<br />
149
Binary Weighted Current Mode Converters<br />
Until now: All possible voltages are generated,<br />
1 out of 2 N voltages is copied to the output<br />
1 1 1<br />
IF b1I<br />
b2I<br />
b3I<br />
b4I<br />
max 1<br />
2<br />
min<br />
Now:<br />
• Current mode, i.e. currents are generated, superposed<br />
and then converted into the output voltage<br />
• Input word is already binary generated binary weighted<br />
currents and superpose them into a current that corresponds<br />
to the input word.<br />
<br />
N I<br />
I<br />
scale switches<br />
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2<br />
4<br />
8<br />
150
Monotonicity in Binary Weighted DACs<br />
Binary weighted converters are not necessarily monotonic<br />
Example:<br />
1<br />
0<br />
1<br />
2<br />
1<br />
1<br />
4<br />
1<br />
1<br />
8<br />
1<br />
1 0 0 0 1<br />
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7<br />
8<br />
6<br />
8<br />
0<br />
1<br />
2<br />
1<br />
1<br />
4<br />
1<br />
1<br />
8<br />
1<br />
7<br />
8<br />
1 0 0 0<br />
6<br />
8<br />
151
Glitches in Binary Weighted DACs<br />
Different delays in the control logic of the switches causes<br />
voltage spikes, i.e. glitches<br />
0 1 1 1 1 0 0 0<br />
0 1 1 1 1 1 1 1<br />
0 1 1 1 0 0 0 0<br />
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1<br />
1<br />
0<br />
0<br />
0<br />
0<br />
0<br />
0<br />
152
Implementation of Binary Weighted DAC<br />
How can we generate binary weighted currents easily?<br />
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153
Implementation of Binary Weighted DAC<br />
For b i = 0 the same current flows, not to VGND but to AGND<br />
30 unit resistors (in binary weighted array)<br />
Not necessarily monotonic<br />
Glitches, if switches do not switch simultaneously<br />
<br />
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154
High number of bits<br />
– large area<br />
High Resolution DAC II<br />
– matching difficult if MSB/LSB ratio is large (currents, resistors)<br />
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155
High number of bits<br />
– large area<br />
High Resolution DAC<br />
– matching difficult if MSB/LSB ratio is large (currents, resistors)<br />
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156
Implementation of Binary Weighted DAC<br />
(with improved resistor ratio)<br />
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157
Implementation of Binary Weighted DAC<br />
(with improved resistor ratio)<br />
(reduced)<br />
<br />
19 unit resistors<br />
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158<br />
158
R-2R-Ladder Network<br />
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159
Implementation of Binary Weighted DAC<br />
(with R-2R-Ladder)<br />
Take R-2R ladder and replace AGND by a virtual ground in<br />
order to collect binary weighted currents<br />
Insert switches (such that node potential is not changed)<br />
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160
Implementation of Binary Weighted DAC<br />
(with R-2R-current divider)<br />
R-2R ladder as current divider<br />
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161
Switched Capacitor Amplifier<br />
(without output reset)<br />
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162<br />
162
SC-Amplifier with Controllable Capacitors<br />
Various variants possible<br />
Gain is altered according to binary input<br />
multiplying DAC (M-DAC)<br />
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163
Thermometer Code Converters<br />
(method to force monotonicity)<br />
# binary thermometer code<br />
b 1 b 2 b 3 d 1 d 2 d 3 d 4 d 5 d 6 d 7<br />
0 0 0 0 0 0 0 0 0 0 0<br />
1 0 0 1 0 0 0 0 0 0 1<br />
2 0 1 0 0 0 0 0 0 1 1<br />
3 0 1 1 0 0 0 0 1 1 1<br />
4 1 0 0 0 0 0 1 1 1 1<br />
5 1 0 1 0 0 1 1 1 1 1<br />
6 1 1 0 0 1 1 1 1 1 1<br />
7 1 1 1 1 1 1 1 1 1 1<br />
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164
Thermometer Code Converters<br />
(method to force monotonicity)<br />
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165
Thermometer Code Converters<br />
(method to force monotonicity)<br />
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166
Hybrid Converter Architectures<br />
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167
Differential Current Steering DAC<br />
Stephan Henzler Advanced Integrated Circuit Design 2011/12<br />
b1 b2 b3 I+ I- Vo<br />
0 0 0 0 I 7/4 I -7/8 RI<br />
0 0 1 1/4 I 6/4 I -5/8 RI<br />
0 1 0 2/4 I 5/4 I -3/8 RI<br />
0 1 1 3/4 I 4/4 I -1/8 RI<br />
1 0 0 4/4 I 3/4 I 1/8 RI<br />
1 0 1 5/4 I 2/4 I 3/8 RI<br />
1 1 0 6/4 I 1/4 I 5/8 RI<br />
1 1 1 7/4 I 0 I 7/8 RI<br />
168
Charge Scaling DAC<br />
Compatibel with switched capacitor circuits<br />
Principle: Divide charge binarily<br />
All caps discharged during 1 (reset phase, no valid output)<br />
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169
Chapter 6<br />
Nyquist Rate<br />
Analog-to-Digital Converters<br />
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170
Analog-to-Digital Converter Families<br />
Architecture Variant Speed Precision<br />
Counting Operation single/dual slope integration low high<br />
Weighted Operation successive approximation<br />
algorithmic converter<br />
w/wo redundancy, callibration<br />
Flash Operation • direct flash<br />
• multi-stage flash<br />
• interpolating flash<br />
• folding flash<br />
Oversampling -modulation, i.e. noise shaping<br />
• discrete time<br />
• continuous time<br />
Sampling frequency can be further increased by<br />
– pipelining<br />
– time interleaving, i.e. parallelization<br />
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medium medium<br />
high low to medium<br />
low to medium high<br />
Time based emerging tbd. tbd.<br />
171
General ADC Model<br />
Linear model<br />
often very useful<br />
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limitations as quantization<br />
noise is de-correlated from<br />
signal<br />
Input signal must change<br />
– sufficiently fast<br />
– sufficiently strong<br />
172
Dual-Slope Analog-to-Digital Converter<br />
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173
Dual-Slope Analog-to-Digital Converter<br />
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174
Iterative Analog-to-Digital Converters<br />
Tracking ADC<br />
Successive Approximation ADC<br />
Algorithmic ADC<br />
Pipeline ADC<br />
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175
Tracking ADCs<br />
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176
Converter with Successive Approximation<br />
What would you ask if you had N questions to find out the<br />
approximate value of the input voltage?<br />
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1. Is it positive or<br />
negative?<br />
NEGATIVE<br />
2. Is it in the upper or<br />
lower negative region?<br />
3. …<br />
UPPER<br />
177
Converter with Successive Approximation<br />
This is a binary search technique:<br />
Partition the interval where the input voltage is located in two sub-intervals and<br />
check whether the voltage lies in the upper or lower part<br />
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178
Converter with Successive Approximation<br />
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offset coded<br />
179
Converter with Successive Approximation (cont)<br />
f s<br />
residue, quantization error<br />
ADC is mainly a DAC and a comparator<br />
(These are the critical building blocks)<br />
Conversion principle:<br />
Make DAC voltage equal to input voltage, minimize error<br />
Depending on the voltage comparison the bits in the SAR<br />
register are iteratively set or reset<br />
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Nf s<br />
180
Modified SAR Algorithm<br />
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Also based on binary search<br />
technique<br />
Comparison against zero<br />
More suited for<br />
implementation,<br />
e.g. charge redistribution<br />
181
Modified SAR Algorithm<br />
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182
Charge Redistribution SAR Converter<br />
Phase I: Input Tracking<br />
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183
Charge Redistribution SAR Converter<br />
Phase II: Hold<br />
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184
Charge Redistribution SAR Converter<br />
Phase III: SAR Evaluation<br />
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185
Charge Redistribution SAR Converter<br />
Phase III: SAR Evaluation<br />
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186
Hybrid SAR Converters<br />
Search can be done with different<br />
references<br />
Same idea as for DACs<br />
– monotonous resistor string for MSBs<br />
– binary weighted cap array for LSBs<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
1. Charge caps to -vin<br />
2. Binary search in resistive<br />
network: vx = -vin + vres<br />
3. Interpolate in between two<br />
subsequent taps of resistor<br />
string by charge redistribution<br />
187
More Details on SAR and Algorithmic ADC<br />
Architectural Considerations on SAR<br />
Pipelined SAR<br />
Redundant SAR<br />
Remember:<br />
The goal is to make this<br />
error voltage<br />
equal to zero<br />
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188
Detailed SAR Architecture<br />
Let’s look at the DAC in detail …<br />
Thermometer Coding<br />
Each DAC has same error contribution<br />
Remainder:<br />
Stephan Henzler Advanced Integrated Circuit Design 2011/12<br />
Aaron Buchwald, Pipelined A/D Converters: The Basics, ISSCC 2008<br />
189
Binary Weighted SAR<br />
Binary weighting is desirable to reduce number of sub-DACs<br />
Remainder:<br />
Error contribution due to DAC mismatch scales with binary<br />
weigting of reference<br />
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190
Binary Weighted SAR<br />
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191
Weighted SAR with Distributed Gain<br />
Binary weighting can be achieved also by using equal DACs<br />
with a single reference voltage but with gain / scaling<br />
elements<br />
Due to scaling MSB DAC is most critical<br />
Linear transformation enables distributed gain<br />
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192
Algorithmic Analog-to-Digital Converter<br />
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Comparator threshold constant<br />
Voltage increment/decrement<br />
constant<br />
remainder is doubled in each<br />
iteration step<br />
accurate x2 circuit required<br />
193
Algorithmic Analog-to-Digital Converter<br />
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194
Algorithmic Analog-to-Digital Converter<br />
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195
Robertson Diagram<br />
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196
Illustration in Robertson Diagram<br />
2. 3. 4.<br />
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1.<br />
5.<br />
197
Algorithmic Analog-to-Digital Converter<br />
Long conversion time<br />
N cycles per inout sample<br />
ADC<br />
DAC<br />
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198
Algorithmic Analog-to-Digital Converter<br />
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199
Voltage Doubling in Algorithmic Converter<br />
V 1<br />
Sample remainder V err together with opamp offset voltage<br />
Amplifier configured as voltage follower<br />
C2 charged to amplifier offset voltage<br />
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V 2<br />
200
Voltage Doubling in Algorithmic Converter<br />
V 1<br />
Disconnect input, discharge C 1<br />
Transfer charge of C 1 to C 2<br />
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V 2<br />
201
Voltage Doubling in Algorithmic Converter<br />
Disconnect C2, charge Q2 unchanged<br />
Sample input again<br />
V 1<br />
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V 2<br />
202
Voltage Doubling in Algorithmic Converter<br />
V 1<br />
Combine charge on C1, offset compensated,<br />
Four clock cycles required!<br />
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V 2<br />
203
Weighted SAR with Distributed Gain<br />
Algorithmic converter in folded implementation<br />
Long conversion time<br />
N x TADC + N x TDAC<br />
Speed-up by insertion of ADC and S&H in each stage<br />
pipelining: high throughput at the price of latency<br />
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204
Pipelined ADC 1<br />
Going for pipelined-ADC means<br />
– cut the feed-back loop<br />
– add a sample-and hold at the output of each stage to store<br />
the remainder, i.e. the stage quantization error<br />
– add a comparator, i.e. coarse ADC at input of each stage<br />
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205
Pipelined ADC 2<br />
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206
High-Speed ADC: Pipeline Processing<br />
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207
Robertson Diagram with Threshold Error<br />
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208
Impact of Comparator Offset on<br />
ADC Performance<br />
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As soon as the residue leaves<br />
the convergence region the<br />
result suffers from major errors<br />
209
Impact of Comparator Offset on<br />
ADC Performance<br />
Comparator offset reflects in<br />
non-linearity of ADC characteristic<br />
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210
Impairments in SAR Algorithms<br />
Finding:<br />
Each error in the amplifier gain or quantizer threshold causes<br />
divergence of the convergence algorithms and thus major<br />
conversion error<br />
How can we make SAR algorithms more robust<br />
Redundancy<br />
Redundant SAR algorithms<br />
Architecture implications<br />
Subranging ADC Pipeline ADC<br />
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211
How can we Strengthen the Algorithm?<br />
Gain and offset errors shift the algorithm out of the<br />
convergence window.<br />
Does an additional threshold help?<br />
No, not necessarily. Important is that the residue is not<br />
scaled back fully.<br />
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212
Redundant SAR Algorithms<br />
Stage quantizer with B bit<br />
(here B=2)<br />
Gain factor = 2 B<br />
Sensitive to thresh. var.<br />
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Stage quantizer with B bit<br />
(here B=2)<br />
Gain factor < 2 B<br />
redundant SAR<br />
not sensitive to thres. var.<br />
213
Redundant Pipeline ADC Algorithm<br />
Redundant algorithm<br />
– Two thresholds<br />
– Gain ( = 2 ) does not scale<br />
residue back to full scale<br />
Stage resolution 1 bit<br />
Information contained<br />
in b i is 1.5 bit<br />
Redundancy<br />
Residue stays in<br />
convergence box even<br />
with strong gain and<br />
offset variations<br />
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214
Subranging Principle<br />
quantization error<br />
Principle: Coarse quantization in frontend ADC and fine<br />
quantization of residue in backend ADC<br />
Pipelining possible (s&h between frontend and backend<br />
Generalization to multi-stage ADC ( pipeline ADC)<br />
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215
Model of Frontend ADC<br />
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216
Linear Model of Subranging ADC<br />
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217
What is the “Digital Result Combiner“?<br />
Output of forward and backward ADC from last slide:<br />
Multiply result of backend ADC by 1/a and add to B out,1<br />
Overall quantization error only depends on quantization error<br />
of backend ADC<br />
Quantization error of backend ADC is scaled by 1/a<br />
Resolution:<br />
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218
Linear Model of Subranging ADC<br />
Effective resolution of frontend ADC is ld(a)<br />
not necessarily the same as the number of bits of B out,1<br />
Analog and digital gain must match, otherwise leakage of<br />
quantization error of frontend ADC<br />
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219
Reconstruction of Signal<br />
Error free reconstruction requires matching between analog<br />
gain a and digital gain a d<br />
In the context of variations this requires calibration<br />
matching<br />
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220
General Pipeline SAR ADC<br />
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221
General Pipeline SAR ADC II<br />
As long as analog and digitals gains match all intermediate<br />
terms vanish<br />
Resolution R:<br />
Gain elements determine resolution, not the stage quantizers<br />
Effective stage resolution:<br />
Last stage must not saturate under all circumstances!<br />
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222
Background Calibration for Stage Gain<br />
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Digital gain is<br />
continuously<br />
adjusted, i.e. even<br />
slow transient<br />
variations are<br />
corrected<br />
Li et al., Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy, TCAS II, 9/2003.<br />
Fu et al., A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters, JSSC, 12/1998<br />
Liu et al., A 15b 40MS/s CMOS Pipelined ADC with Digital Background Calibration, JSSC, 5/2005<br />
many more …<br />
223
Classification of Callibration Techniques<br />
Calibration comprises two phases<br />
– Error estimation<br />
– Error correction<br />
Analog approach additional analog components, noise,<br />
power, distortion, etc.<br />
Digital approach: Works on reults only, i.e. does not interfere<br />
with analog signal processing<br />
Calibration<br />
Foreground Background<br />
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Virtual True<br />
Ginés et al., A Survey on Digital Background Calibration of ADCs, ECCTD, 2009.<br />
224
Summary Pipeline ADC<br />
Stage errors can be tolerated if the residue stays inside the<br />
convergence region<br />
– Minimum requirement is that the residue is back in the convergence region<br />
before the final quantizer)<br />
– Take care for nonlinearity which is not revealed by the linear model<br />
Trade-off sampling frequency – resolution – latency<br />
Number of stages, i.e. number of elements grows linearly<br />
with resolution (not exponentially, ref flash ADC)<br />
Accurate sample-and-hold elements required<br />
(That’s the reason why pipelined time-to-digital converters do not exist)<br />
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225
Nyquist Rate Analog-to-Digital Converters<br />
– Flash Converter –<br />
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226
implemented<br />
as parallel<br />
connection<br />
of 2 unit resistors<br />
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Flash Converter<br />
Generate all switching thresholds in parallel<br />
and compare them to input voltage in parallel<br />
very fast, but high effort in terms of<br />
power, area, noise generation, clock<br />
distribution, input buffering<br />
high speed applications with moderate<br />
resolution<br />
227
Advantages<br />
Properties of Flash ADC<br />
– parallel processing very fast<br />
– no analog post-processing<br />
Disadvantages:<br />
– Huge hardware effort and power consumption (2 N )<br />
– high input capacitance<br />
– synchronous routing of clock signal<br />
Good for high-speed converters with low # of bits<br />
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228
thermometer code<br />
one-hot code<br />
transition detector<br />
Flash Converter<br />
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Thermometer-to-binary<br />
decoder often<br />
implemented in 2 steps<br />
– thermo one-hot<br />
– one-hot binary<br />
Allows for insertion of<br />
bubble correction in<br />
between decoders<br />
229
Bubble Correction in Flash Converter<br />
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230
Bubble Correction in Flash Converter<br />
Bubbles in flash converters:<br />
Source of bubbles:<br />
– noise<br />
– meta-stability<br />
– x-talk<br />
– mismatch<br />
– …<br />
0 0 0 0 0 0 1 1 1 1 1 1<br />
0 0 0 1 0 0 1 1 1 0 1 1<br />
Basic bubble correction with 3-input NAND gate: transition<br />
only detected if more than one high signal occurs.<br />
More complex encoders require to eliminate long distance<br />
errors<br />
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231
Interpolating Flash Converter<br />
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Preamp. with moderate<br />
gain to provide smooth<br />
transition region<br />
Latch for sign detection<br />
Resistive interpolation<br />
to create additional<br />
transition curves in<br />
between 2 regular ones<br />
232
Interpolating Flash Converter<br />
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Interpolation does not work at<br />
boarders<br />
Overrange amplifiers required<br />
233
Interpolating Flash Converter (cont)<br />
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additional series resistors to balance<br />
delays in high-speed interpolating<br />
flash converters<br />
234
Kickback Effect<br />
Especially in flash converters<br />
Clocked comparators produce lots of<br />
noise at their inputs when toggling<br />
from track to latch mode.<br />
Different impedance seen from both<br />
comp inputs<br />
(input drive vs. resistor ladder)<br />
Differential error that may corrupt<br />
next conversion<br />
Decay of error sets max sample rate<br />
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235
Folding ADC<br />
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Similar to flash ADC:<br />
Reuse comparators by<br />
folding voltage back to<br />
reference range<br />
Reduced number of<br />
latches, i.e. suitable for<br />
high-speed ADCs with<br />
med. resolution<br />
Folding blocks cause<br />
nonlinearity<br />
Increased frequency<br />
236
Folding ADC: Operation Principle<br />
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Folding Blocks can be<br />
built by using several<br />
diffpairs connected to the<br />
same load resistors<br />
current is summed up<br />
and converted to the<br />
output voltage<br />
Frequency increases<br />
tough bandwidth<br />
requirements<br />
237
Folding ADC: Basic Schematic<br />
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238
High-Speed ADC: Parallel Processing II<br />
Idea:<br />
Use N (slow) converters in<br />
parallel in a time multiplexed<br />
mode to achieve high-speed<br />
data conversion<br />
Effort:<br />
• N parallel converters<br />
• Sampler and mux at full-speed<br />
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High-Speed ADC: Parallel Processing I<br />
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Chapter 7<br />
Comparators<br />
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Ideal Comparator<br />
Compare input signal to reference and provide binary output<br />
signal<br />
Often same symbol as for opamp<br />
(reasonable as open loop opamp behaves like a comparator)<br />
Comparator is essentially an amplifier with saturation,<br />
ideal comparator means infinite gain in VCVS not realistic<br />
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Static Characteristics of Comparator<br />
Comparator gain<br />
Maximum voltage for negative saturation V DL<br />
Minimum voltage for positive saturation V DH<br />
Comparator resolution: (min. voltage increment, determines comparator gain)<br />
Offset voltage: Horizontal shift of characteristic<br />
Input common mode range<br />
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Dynamic Characteristics of Comparator<br />
Note:<br />
Comparators work in large signal mode of operation<br />
– basic circuit theory to reveal trade-offs and mechanisms<br />
– simulation to determine actual performance figures<br />
Main dynamic performance figure: propagation delay td<br />
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Operational Amplifier as Comparator<br />
Opamp in open-loop configuration is comparator<br />
– asynchronous<br />
– relatively slow due to high gain and stability requirement<br />
– offset error (may be compensated by correlated double sampling,<br />
but this also means synchronous operation)<br />
– Consider DC operating point at input for a reference voltage ≠ 0<br />
– Compensation cap may be disconnected during latching<br />
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OpAmp Comparator Dynamics<br />
Gain-Bandwidth trade-off<br />
– gain determined by desired resolution<br />
– bandwidth determined by desired propagation delay<br />
Amplifier model<br />
Step response<br />
Propagation Delay<br />
(for min step, larger step is faster)<br />
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output signal [norm]<br />
1<br />
0.9<br />
0.8<br />
0.7<br />
0.6<br />
0.5<br />
0.4<br />
0.3<br />
0.2<br />
0.1<br />
-2.0 -0.1<br />
-0.5<br />
Response of Stable 1st Order Linear System<br />
-1.0<br />
-1.0<br />
-0.5<br />
-2.0<br />
-0.1<br />
0<br />
0 2 4 6 8 10<br />
time [AU]<br />
246
Comparator Propagation Delay<br />
Linear mode of operation<br />
Propagation delay for small input signals is determined by<br />
linear small signal dynamics of amplifier<br />
Slew rate limited mode of operation<br />
Propagation delay for large input signals is dominated by<br />
slew rate of opamp output stage<br />
Propagation delay for slew rate limited operation<br />
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Discrete Time Comparators<br />
In some applications comparator function only desired<br />
– during certain intervals<br />
– at certain discrete time instances<br />
Allows for offset compensation via auto-zeroing<br />
and other switched capacitor benefits<br />
Allows for amplifiers in positive feedback configuration<br />
– full level always reached<br />
– gain boosting (reuse one amplifier by cyclic amplification<br />
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Track & Latch Circuit I<br />
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Track & Latch Circuit II<br />
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Principle of Track-and-Latch Stage<br />
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Linear Dynamic of Latch<br />
Linear small signal analysis (ref. Schaltungstechnik 2)<br />
Node voltages<br />
Differential voltage<br />
Propagation delay<br />
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output signal [norm]<br />
1<br />
0.9<br />
0.8<br />
0.7<br />
0.6<br />
0.5<br />
0.4<br />
0.3<br />
0.2<br />
0.1<br />
Response of Instable 1st Order Linear System (Latch)<br />
0.4<br />
0.1<br />
0.01<br />
0<br />
0 0.5 1 1.5 2<br />
time [AU]<br />
2.5 3 3.5 4<br />
252
Latched Comparators I<br />
Standard architecture for high-speed comparators<br />
Latch offset voltage limits resolution of latch-only comparator<br />
scaled down by gain of pre-amplifier<br />
Two step approach:<br />
– analog pre-amplifier stage(s)<br />
– regenerative track and latch stage<br />
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Pre-amplifier:<br />
– 1-3 amplifier stages<br />
Latched Comparators II<br />
– low gain, high-speed<br />
– delay along amplifier chain<br />
– separation of input from latch to reduce loading and avoid<br />
kickback effect<br />
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Track & latch circuit:<br />
Latched Comparators III<br />
– amplifies signal in track mode<br />
– restores (regenerates) signal to full rail in regenerative<br />
latch mode (positive feedback)<br />
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Input Referred Offset of Latch<br />
Input referred offset error of latch stage is reduced by gain A<br />
of pre-amplifier<br />
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Current Mode (CML) Latch<br />
Combines amplifier and<br />
latch functionality<br />
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Memory and Hysteresis in Comparators<br />
Hysteresis:<br />
Switching threshold is different when switching from low to<br />
high and from high to low, respectively.<br />
Useful to avoid bouncing outputs for small (noisy) signals<br />
near comparator threshold<br />
Memory effect:<br />
Kind of hysteresis that causes the comparator decision to be<br />
dependent on previous decisions.<br />
Has to be strongly avoided in Nyquist rate ADCs such as<br />
flash converters.<br />
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Elimination of Memory Effect<br />
Precharge and equalize circuit elements eliminate all<br />
information from previous cycles and decisions<br />
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Switched Capacitor Comparator<br />
Offset compensated<br />
Threshold determined by capacitynce ratio<br />
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Chapter 8<br />
Oversampled Converters<br />
Sigma-Delta Modulator<br />
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Quantization Noise in A/D-Converters<br />
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Linear Model of Quantization Noise<br />
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Quantization Noise and Oversampling<br />
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Quantization Noise and Oversampling<br />
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Quantization Noise and Oversampling<br />
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Feasibility of Oversampling<br />
Goal: Implement ADC (12bit, 44kHz BW) by 1 bit quantizer<br />
with oversampling<br />
12 bit <br />
Same SNR with 1 bit quantizer:<br />
Sampling frequency:<br />
Conclusion: Even medium resolution and low bandwidth<br />
leads to unacceptably high OSR<br />
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Oversampling with Noise Shaping<br />
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First Order Noise Shaping<br />
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First Order Noise Shaping<br />
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First Order Noise Shaping<br />
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Calculation of Signal-to-Noise Ratio<br />
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Calculation of Signal-to-Noise Ratio<br />
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Calculation of Signal-to-Noise Ratio<br />
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274
SC Implementation of 1. Order<br />
ΣΔ Modulator<br />
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275
DAC Accuracy<br />
Linearity error of DAC looks like input signal<br />
DAC needs full accuracy even if quantizer resolution is low<br />
Dynamic element matching<br />
randomizes DAC linearity errors suppressed by OSR<br />
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Comparison Nyquist Rate vs. SD AD<br />
Nyquist Rate ADCs Sigma Delta ADCs<br />
High voltage domain resolution Low voltage domain resolution<br />
in extreme case only 1 bit<br />
Low time domain resolution<br />
f s f Nyquist ( x 2-10)<br />
Low to medium resolution<br />
..(high)<br />
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High time domain resolution<br />
f s >> f Nyquist ( x 64-512)<br />
Very high resolution<br />
up to 20 bit<br />
Result can be directly used Large decimation filter required<br />
One output symbol = one sample One sample distributed over many<br />
output symbols<br />
Medium speed requirements for all<br />
circuit block<br />
Very high speed requirements for<br />
OpAmps, DAC, etc.<br />
277
2. Order Noise Shaping<br />
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278
Calculation of Transfer Functions<br />
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279
Noisespectrum<br />
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Simulation with Matlab/Simulink<br />
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Simulation for OSR=32<br />
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Output Spectrum of ΣΔ-Modulator for<br />
Sinusoidal Input Signal<br />
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Output Spectrum of ΣΔ-Modulator for<br />
Sinusoidal Input Signal<br />
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284
Input Level Dependent SNR<br />
2. Order<br />
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1. Order<br />
285
OSR Dependent Peak-SNR<br />
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286
Tones<br />
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287
power spectral density<br />
0<br />
-50<br />
-100<br />
Tones in Frequency Domain<br />
-150<br />
0 0.1 0.2 0.3 0.4 0.5<br />
frequency/sampling frequency<br />
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Dithering<br />
Reduce the risk of tones by randomizing (artificially) the<br />
comparator input signal: Dithering<br />
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pseudo random signal<br />
affected by noise shaping, i.e.<br />
noise power mainly shifted to high frequencies<br />
SNR only slightly reduced<br />
289
power spectral density<br />
power spectral density<br />
0<br />
-50<br />
-100<br />
-150<br />
0 0.1 0.2 0.3 0.4 0.5<br />
frequency/sampling frequency<br />
0<br />
-50<br />
-100<br />
-150<br />
0 0.1 0.2 0.3 0.4 0.5<br />
frequency/sampling frequency<br />
-100<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
power spectral density<br />
power spectral density<br />
0<br />
-50<br />
-150<br />
0 0.1 0.2 0.3 0.4 0.5<br />
frequency/sampling frequency<br />
0<br />
-50<br />
-100<br />
-150<br />
0 0.1 0.2 0.3 0.4 0.5<br />
frequency/sampling frequency<br />
290
maximum noise peak<br />
Tones<br />
input DC level<br />
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291
3. Order Single-Loop ΣΔ-Modulator<br />
(not cascaded)<br />
Deviation from „ideal“ transfer functions due to stability<br />
requirements<br />
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J. Sauerbrey<br />
292
STF of 3. Order ΣΔ-Modulator<br />
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Noiseshaping of Various ΣΔ-Modulators<br />
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Cascaded ΣΔ-Modulator (Multi stAge noise Shaping)<br />
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Noiseshaping of Various ΣΔ-Modulators<br />
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296
3. Order MASH Structure<br />
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Scaling of ΣΔ-Modulator<br />
1. If inputs of integrators become too large for a significant time<br />
the integrators saturate<br />
non-linearity clipping strong non-linear distortion<br />
(Comparator should be only non-linear component)<br />
2. Exploit full dynamic range for good SNR<br />
Modulator Scaling:<br />
Linear transformation so that<br />
saturation of integrators is avoided<br />
dynamic range is exploited<br />
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hist(S1)<br />
12000<br />
10000<br />
8000<br />
6000<br />
4000<br />
2000<br />
0<br />
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5<br />
S1<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
hist(S2)<br />
9000<br />
8000<br />
7000<br />
6000<br />
5000<br />
4000<br />
3000<br />
2000<br />
1000<br />
0<br />
-4 -3 -2 -1 0 1 2 3 4<br />
S2<br />
299
hist(S1)<br />
x 10<br />
2.5<br />
2<br />
1.5<br />
1<br />
0.5<br />
0<br />
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5<br />
S1<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
hist(S2)<br />
1.8<br />
1.6<br />
1.4<br />
1.2<br />
1<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
x 10<br />
2<br />
0<br />
-1.5 -1 -0.5 0 0.5 1 1.5<br />
S2<br />
300
hist(S1)<br />
2.5<br />
2<br />
1.5<br />
1<br />
0.5<br />
0<br />
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1<br />
S1<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
hist(S2)<br />
2<br />
1.8<br />
1.6<br />
1.4<br />
1.2<br />
1<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
0<br />
-1.5 -1 -0.5 0 0.5 1 1.5<br />
S2<br />
301
Application of ΣΔ-Modulator<br />
in Data Converters (ADC)<br />
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302
ΣΔ-Analog-to-Digital Conversion<br />
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303
Decimation Filtering<br />
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304
Sinc-Filter<br />
Basic low-pass filter averages N subsequent samples:<br />
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Sinc Filter Transfer Functions<br />
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306
Sinc Filter Transfer Functions<br />
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307
Sinc Filter Implementation<br />
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308
Implementation of Sinc-Filter<br />
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309
ΣΔ-Digital-to-Analog Conversion<br />
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310
ΣΔ-Digital-to-Analog Conversion<br />
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311
Multi-Bit Sigma Delta Converter<br />
Replace single-bit quantizer by multi-bit quantizer<br />
Quantizer: Comparator Flash ADC<br />
Feedback DAC: implicit real DAC<br />
Comparator and DAC nonlinearity become critical<br />
Countermeasures: Dynamic element matching, mismatch<br />
shaping, trimming, (digital) correction<br />
Benefit: Reduced OSR and/or better resolution<br />
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Continuous Time Sigma-Delta Converter<br />
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313
Comparison of Discrete- and Continuous<br />
Time Sigma-Delta Converters<br />
Anti-Aliasing Filter Explicit anti-aliasing filter<br />
(AAF) required<br />
Sampling Sampling at input<br />
low jitter & full linearity<br />
required for sampler<br />
Max. frequency and<br />
bandwidth of opamps<br />
Discrete-Time Continuous-Time<br />
All transients must settle<br />
within half of clock cycle,<br />
quickly changing pulses<br />
everywhere in circuit<br />
high bandwidth<br />
requirements limit max.<br />
frequency<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
Implicit filtering<br />
AAF may be obsolete for<br />
some applications<br />
Sampling at comparator, i.e.<br />
within ∑∆-loop<br />
sampling error subject to<br />
noise shaping<br />
Continuous time waveforms<br />
5-10x relaxed bandwidth<br />
requirements<br />
higher clock frequency<br />
possible<br />
314
Comparison of Discrete- and Continuous<br />
Time Sigma-Delta Converters<br />
Jitter Only critical for sampler but<br />
not for rest of sigma delta<br />
modulator<br />
Discrete-Time Continuous-Time<br />
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Very sensitive to timing<br />
variations of clock<br />
Loopdelay Not an issue Very sensitive to loop delay<br />
Switches Signal dependant on<br />
resistance<br />
Signal dependant<br />
comparator delay<br />
No switches<br />
Not an issue Very sensitive causes<br />
harmonic distortion<br />
315
Comparison of Discrete- and Continuous<br />
Time Sigma-Delta Converters<br />
Feedback-DAC Low sensitivity to waveform<br />
settling not critical<br />
Process variations Filter transfer function<br />
based on capacitor ratios<br />
very robust<br />
Discrete-Time Continuous-Time<br />
Stephan Henzler Mixed-Signal-Electronics 2012/13<br />
Very sensitive to waveform<br />
and settling, limits linearity<br />
of modulator<br />
Filter transfer function<br />
depends on RC constants,<br />
i.e. very sensitive to<br />
variations<br />
Noise generation Switching generates noise Reduced supply and ground<br />
noise<br />
316
Web References<br />
Murmann. VLSI Data Conversion Circuits. Stanford University.<br />
Henzler. High-Speed Digital CMOS Circuits. TU Munich.<br />
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