Here - TUM

Mixed-Signal-Electronics 

PD Dr.-Ing. Stephan Henzler 

Stephan Henzler Mixed-Signal-Electronics 2012/13 

1

henzler@tum.de 

Lecturer CV 

Stephan Henzler received the Dipl.-Ing. degree in 

electrical engineering in 2002, the Dr.-Ing. degree in 2006, 

and the habilitation 1 degree in 2010 from the Technische 

Universität München (TUM), Germany. From 2002 to 

2005, he was with the Institute for Technical Electronics, 

Technische Universität München, where he worked on 

low-power digital integrated circuit design and leakage 

reduction techniques. For his dissertation on power 

management and leakage reduction techniques he 

received the Rhode-und-Schwarz outstanding thesis 

award 2007. In 2005, he joined the Advanced Systems 

and Circuits Department of Infineon Technologies AG, 

Munich, where he worked on high-speed/highperformance 

digital integrated circuits, variability in deepsubmicron 

CMOS technologies, and mixed-signal circuit 

design in nanometer CMOS technologies, especially timeto-digital 

converters. In 2010 he joined the wireless mixedsignal 

department of Infineon where he works on mixedsignal 

system and circuit design. Since February 2011 he 

carries on the same responsibilities within Intel. 


2

Stephan’s ambition for this course … 

Simplicity is the Ultimate Sophistication 

Leonardo Da Vinci 


But don’t misunderstand, 

this does not mean that you 

don’t have to exercise! 

3

Course and Online Material 

Lecture notes 

available in the Fachschaft EI (TUM), handout (GIST TUM Asia) 

Online material comprising 

– annotated slides 

– video stream of last years lectures (GIST TUM Asia) 

www.lte.ei.tum.de/homes/henzler 


4

Administratives 

Lecture: Stephan Henzler 

henzler@tum.de 

office hours: during lecture time 

Tutorial: Nasim Pour Aryan 

n.aryan@tum.de 

office hours: during tutorial time 

Exam: in written form, 

Credits: 4.5 ECTS credits (TUM) 

Language: english 


5

The Macroscopic World is Purely Analog 

motion/acceleration 

mechanical force 

sound waves 

light 

electromagnetic 

field 

temperature 

Digital System, e.g. 

- digital communication 

(DSL, GSM, …, LTE) 

- computer equipment 

- multimedia 

(DVD, mp3, camera… ) 

- control application 

(e.g. automotive) 

discrete sequence of 

numbers from a discrete set 

continuous time 

Our environment is always analog … and values 

You just have to investigate the system in-depth! 


sense organs 

sensors/ 

actuators 

time 

even ‘digital’ 

signals on a 

transmission 

channel 

6

The Macroscopic World is Purely Analog 

motion/acceleration 

mechanical force 

sound waves 

light 

electromagnetic 

field 

ADC 

DAC 

Digital System, e.g. 

- digital communication 

(DSL, GSM, …, LTE) 

- computer equipment 

- multimedia 

(DVD, mp3, camera… ) 

- control application 

(e.g. automotive) 

discrete sequence of 

numbers from a discrete set 

The mixed-signal shell is a bridge between 

temperature sense organs 

– the analog environment and the digital signal processing 

– the physical representation (voltage/current) and a mathematical abstraction 


sensors/ 

actuators 

time 

even ‘digital’ 

signals on a 

transmission 

channel 

7

Generic Mixed Signal System 

What means mixed-signal? 

Mixed-signal refers to a system which processes both analog 

and digital signals and which contains converter blocks that 

enable interaction between the two domains. 

Often related to SOC (System-on-Chip) 


8

Topics of MSE Course 

Structure of mixed signal systems and mathematical 

representation of discrete time signals. 

ADC 

discrete time 

discrete states 

discrete time (step function) 

continuous states 


digital discrete time (step function) 

discrete values (states) 

9

Sample & hold circuits 

Topics of MSE Course 

Switched-capacitor circuits 

Data converter fundamentals (ADC, DAC) 

converter parameters and characteristics 

Nyquist rate D/A Converters 

Nyquist rate A/D Converters 

Oversampling Converters: Sigma Delta Converters 

Outlook: More mixed signal building blocks 


10

Recommended Literature 

Analog Integrated Circuit Design. 

David A. Johns 

Ken Martin 


Relevant chapters: 

Chapter 7: 

Comparators. 

Chapter 8: 

Sample-and-Holds 

Chapter 9: 

Discrete Time Signals 

Chapter 10: 

Switched Capacitor Circuits 

Chapter 11: 

Data Converter Fundamentals 

Chapter 12: 

Nyquist-Rate D/A Converters 

Chapter 13: 

Nyquist-Rate A/D Converters 

Chapter 14: 

Oversampling Converters 

11

Additional Literature & References 

Razavi. Principles of Data Conversion System Design. 

Wiley, 1994. 

Allen, Holberg. CMOS Analog Circuit Design. Oxford, 2010. 

Baker, Li, Boyce. CMOS Circuit Desig, Layout, Simulation. 

Wiley, 1997. 

Gregorian, Temes. Analog MOS Integrated Circuits for 

Signal Processing. Wiley 1986. 

Oppenheim. Time Discrete Signal Processing. Oldenbourg 

Norsworthy, Schreier, Temes. Delta-Sigma Data 

Converters. IEEE Press, 1997. 

Schreier, Temes. Understanding Delta Sigma Data 

Converters. IEEE Press 2005. 


12

Constraints of Mixed Signal Circuits in SoC 

PROS CONS 

• Cheap implementation of complex 

signal processing tasks 

• System-on-chip (SOC) 

Small pcb footprint 

• Fast time reference/clock 

• Digitally assisted analog 

• All advantages of digital 

systems, e.g. robustness, noise 

immunity, data storage, 

reconfigurability, efficient highly 

automated design and test 


• Need to build analog circuits in 

digital process, i.e. 

• Devices optimized for high 

switching speed not for analog, 

(e.g. small gm/gds) 

• Transistors with high field 

and short channel effects 

µ(V G), V th(W,L,V DS,V BS), I gate, I DB 

• Signal contamination due to digital 

switching noise, e.g. cross talk, 

supply noise substrate coupling 

• several 100mA digital currents 

• V analog signals 

13

Chapter 1 

Basics of Mixed-Signal Electronics 


14

Generic Structure of Mixed-Signal Systems 

System Perspective 

Circuit Perspective 


15

Representation of Discrete Time Signals and 

Spectral Transformation 

xs(t) = xc(t) X 

= X 


n 

n 

±(t ¡ nT ) 

x(nT )±(t ¡ nT ) 

= X 

x[n]±(t ¡ nT ) 

n 

16



Fourier Transformation 

X(!) = 

generalization 

s = j 

+1 

Z 

¡1 

x(t) = 1 

2¼ 

x(t)e ¡j!t dt 

+1 

Z 

¡1 


X(!)e j!t d! 

X(s) = 

+1 

Z 

¡1 

x(t)e ¡st dt 

Laplace Transformation 

17

Spectral Transformation of Discrete Time Signal 

Insertion of sampled signal in Fourier formula: 

X(!) = 

+1 Z 

X 

¡1 

= X 

Normalization of frequency to sampling frequency: 


n 

n 

x(nT ) 

x(nT )±(t ¡ nT )e ¡j!t dt 

+1 

Z 

¡1 

= X 

x(nT )e ¡j!nT 

n 

e ¡j!t ±(t ¡ nT )dt 

X() = X 

x[n]e ¡jn X(z) = X 

x[n]z ¡n 

n 

FT of discrete sequence 


z = e j = e j!T 

FT of sampled signal 

= !T = 2¼f 

n 

z-Transformation 

fs 

18

Inverse Z-Transformation 

Methods for computation of inverse z-transformation 

– Tabular method 

– Decomposition in partial fractions and tabular method 

– Power series method 

(coefficients correspond to time sequence) 

Formal inversion: 

x[n] = 1 

2¼ 

I 

c X(z)zn¡1 dz 

= X residues of X(z)z n¡1 at poles within C 


19



Meaning of frequency: oscillations per second. 

What is meaning of normalized frequency Ω? 


Ω = angular change from sample to sample 

20



Spectrum of a sampled signal: 

s(t) = X 

±(t ¡ nT ) $ S(!) = 2¼ 

T 

n 

xs(t) = xc(t) ¢ s(t) $ 

Sampling means multiplication 

of continuous time signal with 

pulse train 

X 


k 

±(! ¡ k!s) !s = 2¼ 

T 

Xs(!) = 1 

2¼ Xc(!) ¤ S(!) 

= 1 

T Xc(!) ¤ X 

= 1 

T 

X 

k 

In frequency domain this translates 

into convolution of signal spectrum 

with spectrum of pulse train. 

This is simply a copy and shift of 

the spectrum to multiples of the 

sampling frequency 

k 

Xc(! ¡ k!s) 

±(! ¡ k!s) 

21




Aliasing occurs if mirror spectra overlap 

22

low-pass 

low-pass 

low-pass 

Aliasing in the Frequency Domain 

low-pass filtering 


t 

t 

t 

theoretical case as brick wall 

filter would be required 

t 

t 

t 

23

amplitude fsampling = 1 f signal,1 = 0.22 

1 

0.8 

0.6 

0.4 

0.2 

0 

-0.2 

-0.4 

-0.6 

-0.8 

-1 

Sampling and Aliasing 1 

0 5 10 15 

samples 


24

amplitude fsampling = 1 f signal,2 = 0.22 + fsampling 

1 

0.8 

0.6 

0.4 

0.2 

0 

-0.2 

-0.4 

-0.6 

-0.8 

-1 


0 5 10 15 

samples 


25

amplitude 

1 

0.8 

0.6 

0.4 

0.2 

0 

-0.2 

-0.4 

-0.6 

-0.8 

-1 


Only with the Nyquist criterion it is assured that the samples 

represent the signal unambiguously 

0 5 10 15 

samples 


26

Anti Aliasing Filter 

No brick wall filter with infinitely steep transition band 

Real filters have a transition band 

– Nyquist rate is a theoretical limit but not feasible 

– Tradeoff between sample rate and filter order 


27

Practical Sampling: Sample & Hold 

Remember: All realizable signals have 

– finite slope (dx/dt) 

– finite pulse width, i.e. finite bandwidth 

– finite value 


t 

t 

t 

ideal sampling 

step function 

alternative solution 

28



– finite slope 

– finite pulse width 

– finite bandwidth 


Hence sampling means always SAMPLE & HOLD 


29

Sampling with Finite Pulse Width 

x sh(t) = xs(t) ¤ h(t) 

= 

x sh(!) = 1 

¿ 

= 1 

¿ 

1X 

n=¡1 

+1 

Z 

¡1 

1X 

= ¡ 1 

j!¿ 

xc[n] 1 

¿ [¾(t ¡ nT ) ¡ ¾(t ¡ nT ¡ ¿)] 

1X 

n=¡1 

n=¡1 

1X 

xc[n] 

n=¡1 


xc[n] [¾(t ¡ nT ) ¡ ¾(t ¡ nT ¡ ¿)] e ¡j!t dt 

nT +¿ 

Z 

nT 

e ¡j!t dt 

xc[n] h 

e ¡j!ti nT +¿ 

nT 

(t) 

t 

30

Xsh(!) = ¡ 1 

j!¿ 

Sampling with Finite Pulse Width 

= 

1X 

n=¡1 

Distortion of base band and damping of mirror spectra 

– visible in DAC 

– not visible in ADC 

1X 

n=¡1 

xc[n]e ¡j!nT 


xc[n] ³ 

e ¡j!nT e ¡j!¿ ´ 

¡ e 

¡j!nT 

1 

j!¿ 

= Xs(!)e ¡1 2j!¿ ej 1 2 !¿ ¡ e ¡j 1 2 !¿ 

2j 1 2 !¿ 

= Xs(!)e ¡j 1 2 !¿ sin ³ 1 

2 !¿ ´ 

³ 

´ 

1 ¡ e 

¡j!¿ 

ideal sampling X S() impact of hold 

1 

2 !¿ 

31




32


X(s) = 

Relation Between s- and z-Plain 

Fourier Transformation: 

+1 Z 

X(!) = 

¡1 

x(t)e ¡j!t dt 

LaPlace Transformation: z-Transformation: 

+1 Z 

1X 

j 

¡1 

x(t)e ¡st dt X(z) = 

s 

 

z = e j!T 

discrete 

signals 


Im(z) 

1X 

n=¡1 

x(nT )e ¡j!nT 

normalization 

& 


n=¡1 

z 

x[n]z ¡n 

Re(z) 

33

Downsampling 

Intuitive view: 

If the analog signal was sampled directly with the low rate we 

would get every 1 out of L samples 

remove all other samples, keep only 1 out of L 

Additional information: If there is noise between the repeated signal spectra, or if the Nyquist criterion cannot be guaranteed for the 

down-sampled signal an additional filtering is required (low pass). However, it is sufficient to compute one out of L samples. 


34

Downsampling II 

Mathematically downsampling comprises two steps: 

– digital sampling, i.e. multiplication with a periodic 

1,0,0, …, 0, 1, 0, … sequence 

– dropping of all zero weighted samples and scaling of 

frequency axis 

In spectrum this means a copy and shift of the already 

periodic signal 

risk of aliasing 

eventually AAF prior to downsampling (decimation filter) 


Spectrum of sampling fcunction: 

35

decimation filter 

Downsampling III 

Down-sampling requires, that there is no signal energy in 

between baseband and mirror spectra (e.g. noise) 

In general this is not the case, so down-sampling may cause 

aliasing 

To avoid aliasing a low pass filter is required in front of downsampling 

block Decimation Filter (Decimator) 


36

Upsampling 


imaging 

Additional information: Fractional sample rate conversion is up-sampling combined with down-sampling. Low-pass filters 

may be shared. Compute only what is necessary! 

37

Upsampling II 

Zero padding results in higher sampling rate 

However, this does not mean that mirror spectra occur only 

at multiples of the sampling frequency 

Imaging, i.e. replica in between 0..2 

Low pass filter removes images 

– Result in frequency domain: Replica only at k x f s 

– Result in time domain: Zeros move on real signal curve 


38

Fractional Sample Rate Conversion 

Purpose: Change sample rate by a non-integer factor L/M 

Two possibilities: 

– Up-sampling by L, down-sampling by M 

– Down-sampling by M, than up-sampling by L 

The order of up- and down-sampling may be exchanged 

without any change in the input/output behavior if the 

decimation factor M and the interpolation factor L are 

relatively prime. 


39

Components of a Mixed Signal System 

Structure of mixed signal systems and mathematical 

representation of discrete time signals. 


40

Example for Simple Anti Aliasing Filter 


41

Supply Voltages of Mixed Signal Circuits 

General case: use of bipolar signals 

VDD 

AGND 

VSS 

most positive potential 

positive signals 

analog ground / reference voltage 

(reference point for analog signals) 

negative signals 

most negative potential 


+2V 

Even more complex supply concepts in use check for available voltages and definitions before starting with design 

0V 

-2V 

4V 

2V 

0V 

42

Transistor Description (for hand calculations) 


43

Condutance G 

V SS 

MOS Transistor as Switch 


V DD 

44

Chapter 2 

Sample and Hold Circuits 


45



– finite slope 

– finite pulse width 



t 

t 

t 

46

Sample & Hold Circuit 


47

Sample & Hold Circuit (cont) 

1. Finite rise-time / finite bandwidth due to RC constant 

2. Amplifier dynamics 

(finite settling time, overshoot, ringing) 

Driving amplifier sees a varying load impedance 

(RC input isolation can reduce effect) 


48

Sample & Hold: Clock Feed-Through 

3. Clock feed-through due to capacitive coupling. 


49

Sample & Hold: Charge Injection 

4. Charge Injection: mobile carriers are removed 

1:1 distribution is a approximation for fast switching 


50

5. 

6. Clock jitter 

Sample & Hold Circuit (cont) 

7. Droop in hold mode: leakage currents discharge hold cap 

8. Linearity 


51

S&H Output Signal 


52

Impact of Jitter on S&H Performance 

Consider a sinusoidal signal 

Signal power 

Rate of change 

Jitter = random variation of sampling instance 

Sampling error: 


53

Impact of Jitter on S&H Performance 

Noise power resulting from sampling error 

Signal-to-Noise Ratio 

maximum achievable SNR for given jitter 

frequency dependent, i.e. the larger the bandwidth the higher 

the clock requirements 


54

Noise due to jitter: 

Jitter Effect Analysis 

A noise floor which scales with signal frequency and 

amplitude is an indication for dominant aperture and jitter 

effects. 


55

Impact of Offset-Voltage 

Offset voltage of opamp is modeled as voltage source in 

series to input terminal 

V o 

Offset voltage is directly visible at output terminal 


56

S&H with Correlated Double Sampling 


57

Noise in Discrete Time Systems 

Noise is a random process statistical description is required 

time domain: noise signal a(t) 

frequency domain: power spectral density 


58

Noise of Sampled Signals: kT/C-Noise 

White noise with power spectral density is 

low-pass filtered: 

Noise power: 

independent on R 

Remarks: 

• Sampling makes this a little bit more complicated as noise is a wide band signal so there is aliasing of replica 

spectra. However, the noise power in the baseband is still kT/C 

• This is only a lower bound of noise power, buffers contribute also to overall noise power 


59

Assumption: 

– 

– 

Noise Reduction Techniques 

Average over 4 samples 

Generally: 


60

Closed Loop Track & Hold Circuit 1 

Basic sampling circuit is embedded in feedback loop 

– Very high input impedance 

– Reduction of non-idealities (e.g. buffer offset) by loop gain 

– Loop must be designed stable speed degradation 

– Feedback is broken during hold mode 

• Input opamp saturates 

offset not canceled 

• Long slewing time when circuit returns to track mode 


not critical wrt. offset errors 

61


Hold mode: 

Input opamp is configured as voltage follower 

fast settling when circuit returns to track mode 


62


Storage capacitor is shifted to feedback loop of output 

amplifier (integrator) 

Swing across switch is always near to AGND 

Error injection becomes nearly signal independent (pedestal error) 

No appertur jitter 

Input opamp is grounded during hold phase 

fast settling when switched to track mode 

signal feedthrough is minimized 

Reduced speed due to stability requirements 


63


Additional error replica to avoid the pedestal error 


64

Summary Sample & Hold Circuits 


65

Chapter 3 

Switched Capacitor Circuits 


66

Resistor Realizations in MOS Technologies: Poly-Resistor 


Sheet resistance: 

200-400Ω□ 

(metal

Resistor Realizations in MOS Technologies: Diffusion Resistor 

Sheet resistance: 50-150Ω□ 

Highly variable resistance (up to +/- 20%) 

Parasitic diode 

High parasitic capacitances 


68

Resistor Realizations in MOS Technologies 


L 

R 

R[] 

Wd 

Sheet resistance: 

Poly: 200-400Ω□ 

Diffusion: 50 -150Ω□ 

Metal:

Effect of Resistor between two Nodes 

continuous time point-of-view discrete time point-of-view 


70

Switched Capacitor Resistor Emulation 1 


71

Switched Capacitor Resistor Emulation 2 


72

Resistor Equivalents 


73

Non-Overlapping Multiphase Clocking 

both clocks active at the same time 

would cause short circuit currents 


74

Parameter Variations in SC Circuits 1 

What is the variation of a RC time constant? 

i.e. the relative error of the time constant is equal to the sum of 

the relative error of the resistance and the capacitance 


75

Parameter Variations in SC Circuits 2 

What happens for the switched-capacitor equivalent? 

i.e. the relative error of the time constant is equal to the relative 

error of a capacitance ratio 

very small if matching is considered in layout 


76

Implementation of Integrated Capacitors 


77

Alternative Capacitor Implementation 

Junction capacitance 

– Parasitic diode leakage 

– Voltage and temperature dependent 

MOS capacitance 

– MOS transistor in accumulation or inversion 

– Alternatively: gate over diffusion 

– Strongly non-linear 

– Very high capacitance/area 

– God for decoupling 

Vertical parallel plate capacitor 

– Matrix of wires exploiting vertical and lateral capacitance 

– Ref. next slide 


78

Vertical Parallel Plate Capacitor 


Kim, VLSI Symposium 2003 

79

Limitations of SC-Equivalence 

Continuous Time RC-Low-Pass 


80



S 1 and S 2 are 

closed alternately 

81


Switched Capacitor Low-Pass 

z-Transformation: 


82


Switched Capacitor Equivalence 


83

Switched Capacitor Integrators 


84

Switched Capacitor Integrators 


85

Analysis of Switched-Capacitor Circuits 

– SC-Cookbook – 

Mark polarity of all capacitors (arbitrarily) 

Do not change this polarity during the analysis 

Draw equivalent circuit for each clock phase 

Charge balance analysis for full cycle 

– assume steady state conditions for each time step 

– compute ∆Q that occurs during phase transitions 

z-transformation 

Calculate transfer function 

Evaluate transfer function on unit circle of z-plane 


86

z-Transformation 

Approximation on unit circle 

Spectral Analysis 


87

Spectral Analysis (cont.) 


88

Analysis of Switched-Capacitor Circuits 

– SC-Cookbook – 

Mark polarity of all capacitors (arbitrarily) 

Do not change this polarity during the analysis 

Draw equivalent circuit for each clock phase 

Charge balance analysis for full cycle 

– assume steady state conditions for each time step 

– compute ∆Q that occurs during phase transitions 

z-transformation 

Calculate transfer function 

Evaluate transfer function on unit circle of z-plane 


89

Time Domain Behavior 


90

Impact of Parasitic Capacitances 

C p1||C 1 direct impact on transfer behavior 

C p2 shorted no impact 

C p3 shorted between GND and VGND 

C p4 at opamp output negligible impact 

H 

C 

1 p1 

z 

1 


C 

C 

2 

z 

1 

z 

1 

91

Alternative Integrator Architectures 

Sign of transfer function can be changed by switching the 

control signal of the switches. 

Less sensitive to parasitic capacitances 


92

Switched Capacitor Amplifier 


93

Switched Capacitor Amplifier: Impact of Offset 


94

SC Amplifier: Output Signal 


opamp offset 

95


(without output reset) 


96

Superposition Theorem in SC Circuits 


97

Chapter 4 

Data Converter Fundamentals 

"He who loves practice without theory is like the 

sailor who boards ship without a rudder and 

compass and never knows where he may cast“ 

Leonardo Davinci 


98

Ideal Digital-to-Analog Conversion 


99

DAC Offset Error 


100

DAC Gain Error 


101

Digital-to-Analog Converter Model 

ideal model 1 st order model 

Gain of ideal converter depends on interpretation of DAC 

input bits. Here, a fractional interpretation is used. 


102

Ideal Analog-to-Digital Conversion 


103

Analog-to-Digital Converter Model I 

Depending on implementation quantization block can be 

– round function 

– floor function 

– ceil function 


104

Quantization in A/D-Converters 


105


Consider one saw tooth, e.g. 

Mean quantization error: 

Power of quantization error: 


106


Signal-to-(Quantization)-Noise Ratio S(Q)NR: 


107

ADC Offset Error 


108

ADC Gain Error 


109

Analog-to-Digital Converter Model II 


110

Non-Linearity in Data Converters 


111

Example of Non-Linear Transfer Characteristic 

x 

non-linear 

system 


y 

112

Nonlinearity in Data-Converters 


Accuracy: 

The absolute inaccuracy is 

defined as the maximum 

deviation of the actual analog 

value from the ideal one. It 

includes offset, gain and 

linearity errors and may be 

different for every individual 

quantization value. 

The relative inaccuracy is 

defined as the deviation that 

remains after offset and gain 

error have been removed. 

113

DAC Nonlinearity: Integral Nonlinearity 

Integral Nonlinearity (INL) Error: 

The INL error is defined as the deviation of each analog value from a straight 

line. If the straight line through the endpoints of the converter’s transfer curve 

is chosen (left) as reference, the INL equals the relative inaccuracy. 

Alternatively a regression line can be used as reference (right). It depends on 

the application which definition should be applied. 


114

DAC Nonlinearity: Differential Nonlinearity 


Differential Nonlinearity (DNL): 

Deviation of the analog step size 

from 1VLSB (after removal of gain 

and offset error). Like the INL the 

DNL value is defined individually 

for each digital word 

Monotonicity: 

The output signal of a monotonic 

D/A converter increases or 

remains at least unchanged as 

the input signal increases. 

115

ADC Nonlinearity: Inaccuracy 


Accuracy: 

The absolute inaccuracy is 

defined as the maximum 

deviation of the actual analog 

value from the ideal one. It 

includes offset, gain and 

linearity errors and may be 

different for every individual 

quantization value. 

The relative inaccuracy is 

defined as the deviation that 

remains after offset and gain 

error have been removed. 

116

ADC Nonlinearity: Integral Nonlinearity 


Integral Nonlinearity (INL): 

The INL error is defined as the 

deviation of each analog value 

from a straight line (after 

removal of gain and offset error). 

If the straight line through the 

endpoints of the converter’s 

transfer curve is chosen as 

reference, the INL equals the 

relative inaccuracy. Alternatively 

a regression line can be used as 

reference. It depends on the 

application which definition 

should be applied. 

117

ADC Nonlinearity: Differential Nonlinearity 


Differential Nonlinearity (DNL): 

Deviation of the analog step size 

from 1VLSB (after removal of gain 

and offset error). Like the INL the 

DNL value is defined individually 

for each digital word 

Missing Codes: 

If one step vanishes completely 

the ADC is said to have a missing 

code. In practice the criterion for a 

missing code is a step width 

smaller than 0.1 x VLSB 

118

Dynamic ADC Measurement 

ADC converter characteristics 

describe static measurements 

In dynamic measurements a input 

voltage waveform (usually a sine signal) 

is converted continuously and 

analyzed in the frequency domain. 

(much more realistic, noise, crosstalk, etc.) 


119

[FS] 

Interpretation of the Output spectrum 

noise floor 

test signal 

A sin(wt) 

harmonics 


Robertson, ISSCC, 2002 

0.5 x 

sampling 

frequency 

120

Harmonic Distortion Caused by Nonlinearity 

Nonlinearity causes harmonic distortion 

Spectrum allows computation of 

– signal power 

– power of harmonic components 

– noise power 

Signal-to-Noise Ratio: 

 

SNR 10 

log 

 

10 

 

Signal-to-Noise-and-Distortion Ratio 

 

SNDR 10 

log 

 

10 

 

signal 

noise 


P 

noise 

P 

P 

P 

 

signal 

P 

 

 

 

 

harmonics 

 

 

 

 

121

Harmonic Distortion Caused by Nonlinearity 

Total Harmonic Distortion (THD) 

THD 

 

20 

log10 

Second Harmonic Distortion (SHD) 

SHD 

V 

2 

V 

2 

V 

2 

 


 

 

 

 

20 

2 

log10 

 

 

 

 

3 

V 

V 

V 

1 

2 

1 

 

 

 

 

4 

 

 

 

 

 

122

Effective Number of Bits 

An ideal ADC suffers only from quantization noise 

SNR 

SQNR 6. 02dB 

N 1. 

76dB 

Actual ADCs have lots of impairments (noise, nonlinearity) 

that limit the effective resolution. 

Effective number of Bits: 

ENOB 

SNDR 

6. 

02 

1. 

76 

dB 

Note: The number of bits coming out of an ADC doesn‘t say 

anything about the actual resolution 


 

dB 

123

Signal-to-Noise Ratio over Input Signal 


124

Other Useful Figures in Mixed-Signal 

Crest Factor = Peak-to-Average Ratio 

Measure for dynamics of a signal defined by the quotient of 

the peak amplitude and the RMS value 

C 

max 

x( 

t) 

 

2 

x ( t) 

ADC Figure-of-Merit: 

Measure for the efficiency of an ADC 

FOM 

power 

frequency 2 

ENOB 


 

125

Why is Linearity so Important? 

Let‘s consider a basic example of third order non-linearity 

The following equalities are useful 

Harmonic Distortion: 

A single tone transforms into a dc offset and multiple tones at 

multiples of the original input frequency 


x 

non-linear 

system 

y 

126

Non-Linearity Gain Compression 

Consider only the fundamental (i.e. for low amplitude) 

For small amplitude A the gain of the system is a 1 

With increasing amplitude A, the high order term becomes 

noticeable, i.e. the gain becomes 

For a compressive system 

(a 3

Superposition of two Frequencies 


128

Superposition of Two Frequencies 


129

Non-Linearity Desensitization 

Consider superposition of weak signal and a strong interferer 

Strong signal causes large excitation around operating point 

effective gain reduction 

Small signal gain may become even zero 

blocking 


130

Non-Linearity Cross Modulation 

Consider again superposition of weak signal and a strong 

interferer, but now with modulation of interferer 

Amplitude variation m 2 may be either noise or modulation 

Signal in band around 1 

Modulation/noise of the carrier 2 is transferred 1 

Effect occurs if multiple channels are processed by same 

non-linear system, e.g. non-linear amplifier in wireless base 

station 


131

Non-Linearity Intermodulation 

Harmonics can be used to quantify the non-linearity of mixedsignal 

system. 

If the system is frequency selective, e.g. a low-pass filter 

some or even all harmonics are damped 

system seems to be less non-linear than it actually is. 

Measure non-linearity in band of interest, i.e. without 

damping effects Intermodulation Experiment 

Two-Tone Test: 


132


Two tones passing a non-linear system result in 

– Harmonics of first frequency 

– Harmonics of second frequency 

– Intermodulation products (caused by mixing signals) 

If the frequency difference is small, i.e. 2 - 1


Intermodulation distortion = 3 rd IM product / fundamental 

(Amplitude must be known for interpretation) 

Assume small amplitudes, i.e. the amplitude of the 

fundamental can be expressed by a 1A and the IM3 is 3/4a 3A 3 

Third order intercept point describes the amplitude where the 

IM3 equals the fundamental 

(Hypothetical as for high amplitudes higher order non-linearity becomes noticeable, i.e. meas. is done for small amplitudes followed by extrapolation) 


134

Non-Linearity: Further Reading 

Recommended Literature: 

– Razavi. RF Microelectronics. Prentice Hall. 

– Robertson. Specification and Figures of Merit for 

Mixed-Signal Circuits. ISSCC Tutorial 2002. 

– Razavi. Principles of Data Conversion System Design. 

Wiley, 1994. 


135

Binary Number Representation 

# # 

normalized 

Sign 

magnitude 

1‘s 

complement 


2‘s 

complement 

Offset 

binary 

+7 +7/8 0111 0111 0111 1111 

+6 +6/8 0110 0110 0110 1110 

+5 +5/8 0101 0101 0101 1101 

+4 +4/8 0100 0100 0100 1100 

+3 +3/8 0011 0011 0011 1011 

+2 +2/8 0010 0010 0010 1010 

+1 +1/8 0001 0001 0001 1001 

+0 0 0000 0000 0000 1000 

-0 0 1000 1111 

-1 -1/8 1001 1110 1111 0111 

-2 -2/8 1010 1101 1110 0110 

-3 -3/8 1011 1100 1101 0101 

-4 -4/8 1100 1011 1100 0100 

-5 -5/8 1101 1010 1011 0011 

-6 -6/8 1110 1001 1010 0010 

-7 -7/8 1111 1000 1001 0001 

-8 -8/8 1000 0000 

136

Chapter 5 

Nyquist Rate 

Digital-to-Analog Converters 


137

Nyquist Rate Digital-to-Analog Converters 

V 

out 

Basic Idea: 

• Generate all possible voltages which are possible 

according to eq. 1 

• Use switches to connect the voltage selected by B in to 

the output 


ref 

in 

ref 

1 

2 

N 

b 2 b 

2 

b 

V B V 

2 

1 

2 

N 

138

max value 

bus 

voltage follower 

strictly monotonic 

3-Bit Resistor String Converter 


Generate all possible voltages with 

resistive voltage divider 

Switches = NMOS transistors 

Transmission gates enable 

– higher voltage range 

– but higher parasitic cap, area 

(layout more complicated) 

Buffer experiences high input 

voltage variation 

Slow due to buffer and analog mux 

How fast does the DAC settle 

139

Prerequisites: 

– one input only 

Elmore Delay 

– caps between network node and ground only 

– no resistive loops 

W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, 1948. 


140

Elmore Delay (cont.): Path Resistance 

There is exactly one resistive path from a network node i to 

the input s. 

The sum of all resistances along this path is the path 

resistance R ii, e.g. R 44 = R 4 + R 3 + R 1 


141

Elmore Delay: Shared Path Resistance 

The shared path resistance R ik is the sum of all resistances 

along the joint sub-path of the two paths s i and s k. 

Example: R i4 = R 1 + R 3 


142

Elmore Delay (cont): Delay Approximation 

Elmore delay: 

First order approximation of the delay after which a voltage 

step at the input s can be observed at the output i. 


SS 2008 

143

Elmore Delay (cont): Delay Approximation 

Elmore delay: 

Useful for 

– Estimation of wire delay 

– Estimation of DAC settling time 

– … 


SS 2008 

144


Resistor String Converter 

145


(with pass-gate decoder) 

Stephan Henzler Mixed-Signal-Electronics 2012/13 146

Normalized Delay 

300 

250 

200 

150 

100 

50 

Delay Comparison 

0 

0 2 4 6 8 10 12 14 16 

Number of Bits 


string 

tree 

147

Folded Resistor String Converter 

Combine the advantages of both converters: 

(low effort for decoder, small load cap.) 

Access scheme as in memories: 

MSBs select row 

LSBs select column 

2 

N 

2 

transistors at output bus 

all bitlines are charged 


148


Multi-Stage 


Subdivde voltage range in 

coarse sub-intervals first 

Copy the respective voltage 

interval 

Fine interpolation of the 

copied interval 

• if opamps match the converter is monotonic 

• less resistors 

• reduced area and power 

149

Binary Weighted Current Mode Converters 

Until now: All possible voltages are generated, 

1 out of 2 N voltages is copied to the output 

1 1 1 

IF b1I 

b2I 

b3I 

b4I 

max 1 

2 

min 

Now: 

• Current mode, i.e. currents are generated, superposed 

and then converted into the output voltage 

• Input word is already binary generated binary weighted 

currents and superpose them into a current that corresponds 

to the input word. 

 

N I 

I 

scale switches 


2 

4 

8 

150

Monotonicity in Binary Weighted DACs 

Binary weighted converters are not necessarily monotonic 

Example: 

1 

0 

1 

2 

1 

1 

4 

1 

1 

8 

1 

1 0 0 0 1 


7 

8 

6 

8 

0 

1 

2 

1 

1 

4 

1 

1 

8 

1 

7 

8 

1 0 0 0 

6 

8 

151

Glitches in Binary Weighted DACs 

Different delays in the control logic of the switches causes 

voltage spikes, i.e. glitches 

0 1 1 1 1 0 0 0 

0 1 1 1 1 1 1 1 

0 1 1 1 0 0 0 0 


1 

1 

0 

0 

0 

0 

0 

0 

152

Implementation of Binary Weighted DAC 

How can we generate binary weighted currents easily? 


153


For b i = 0 the same current flows, not to VGND but to AGND 

30 unit resistors (in binary weighted array) 

Not necessarily monotonic 

Glitches, if switches do not switch simultaneously 

 


154

High number of bits 

– large area 

High Resolution DAC II 

– matching difficult if MSB/LSB ratio is large (currents, resistors) 


155

High number of bits 

– large area 

High Resolution DAC 

– matching difficult if MSB/LSB ratio is large (currents, resistors) 


156


(with improved resistor ratio) 


157


(with improved resistor ratio) 

(reduced) 

 

19 unit resistors 


158 

158

R-2R-Ladder Network 


159


(with R-2R-Ladder) 

Take R-2R ladder and replace AGND by a virtual ground in 

order to collect binary weighted currents 

Insert switches (such that node potential is not changed) 


160


(with R-2R-current divider) 

R-2R ladder as current divider 


161


(without output reset) 


162 

162

SC-Amplifier with Controllable Capacitors 

Various variants possible 

Gain is altered according to binary input 

multiplying DAC (M-DAC) 


163

Thermometer Code Converters 

(method to force monotonicity) 

# binary thermometer code 

b 1 b 2 b 3 d 1 d 2 d 3 d 4 d 5 d 6 d 7 

0 0 0 0 0 0 0 0 0 0 0 

1 0 0 1 0 0 0 0 0 0 1 

2 0 1 0 0 0 0 0 0 1 1 

3 0 1 1 0 0 0 0 1 1 1 

4 1 0 0 0 0 0 1 1 1 1 

5 1 0 1 0 0 1 1 1 1 1 

6 1 1 0 0 1 1 1 1 1 1 

7 1 1 1 1 1 1 1 1 1 1 


164




165




166

Hybrid Converter Architectures 


167

Differential Current Steering DAC 

Stephan Henzler Advanced Integrated Circuit Design 2011/12 

b1 b2 b3 I+ I- Vo 

0 0 0 0 I 7/4 I -7/8 RI 

0 0 1 1/4 I 6/4 I -5/8 RI 

0 1 0 2/4 I 5/4 I -3/8 RI 

0 1 1 3/4 I 4/4 I -1/8 RI 

1 0 0 4/4 I 3/4 I 1/8 RI 

1 0 1 5/4 I 2/4 I 3/8 RI 

1 1 0 6/4 I 1/4 I 5/8 RI 

1 1 1 7/4 I 0 I 7/8 RI 

168

Charge Scaling DAC 

Compatibel with switched capacitor circuits 

Principle: Divide charge binarily 

All caps discharged during 1 (reset phase, no valid output) 


169

Chapter 6 

Nyquist Rate 

Analog-to-Digital Converters 


170

Analog-to-Digital Converter Families 

Architecture Variant Speed Precision 

Counting Operation single/dual slope integration low high 

Weighted Operation successive approximation 

algorithmic converter 

w/wo redundancy, callibration 

Flash Operation • direct flash 

• multi-stage flash 

• interpolating flash 

• folding flash 

Oversampling -modulation, i.e. noise shaping 

• discrete time 

• continuous time 

Sampling frequency can be further increased by 

– pipelining 

– time interleaving, i.e. parallelization 


medium medium 

high low to medium 

low to medium high 

Time based emerging tbd. tbd. 

171

General ADC Model 

Linear model 

often very useful 


limitations as quantization 

noise is de-correlated from 

signal 

Input signal must change 

– sufficiently fast 

– sufficiently strong 

172

Dual-Slope Analog-to-Digital Converter 


173

Dual-Slope Analog-to-Digital Converter 


174

Iterative Analog-to-Digital Converters 

Tracking ADC 

Successive Approximation ADC 

Algorithmic ADC 

Pipeline ADC 


175

Tracking ADCs 


176

Converter with Successive Approximation 

What would you ask if you had N questions to find out the 

approximate value of the input voltage? 


1. Is it positive or 

negative? 

NEGATIVE 

2. Is it in the upper or 

lower negative region? 

3. … 

UPPER 

177


This is a binary search technique: 

Partition the interval where the input voltage is located in two sub-intervals and 

check whether the voltage lies in the upper or lower part 


178



offset coded 

179

Converter with Successive Approximation (cont) 

f s 

residue, quantization error 

ADC is mainly a DAC and a comparator 

(These are the critical building blocks) 

Conversion principle: 

Make DAC voltage equal to input voltage, minimize error 

Depending on the voltage comparison the bits in the SAR 

register are iteratively set or reset 


Nf s 

180

Modified SAR Algorithm 


Also based on binary search 

technique 

Comparison against zero 

More suited for 

implementation, 

e.g. charge redistribution 

181

Modified SAR Algorithm 


182

Charge Redistribution SAR Converter 

Phase I: Input Tracking 


183


Phase II: Hold 


184


Phase III: SAR Evaluation 


185


Phase III: SAR Evaluation 


186

Hybrid SAR Converters 

Search can be done with different 

references 

Same idea as for DACs 

– monotonous resistor string for MSBs 

– binary weighted cap array for LSBs 


1. Charge caps to -vin 

2. Binary search in resistive 

network: vx = -vin + vres 

3. Interpolate in between two 

subsequent taps of resistor 

string by charge redistribution 

187

More Details on SAR and Algorithmic ADC 

Architectural Considerations on SAR 

Pipelined SAR 

Redundant SAR 

Remember: 

The goal is to make this 

error voltage 

equal to zero 


188

Detailed SAR Architecture 

Let’s look at the DAC in detail … 

Thermometer Coding 

Each DAC has same error contribution 

Remainder: 


Aaron Buchwald, Pipelined A/D Converters: The Basics, ISSCC 2008 

189

Binary Weighted SAR 

Binary weighting is desirable to reduce number of sub-DACs 

Remainder: 

Error contribution due to DAC mismatch scales with binary 

weigting of reference 


190

Binary Weighted SAR 


191

Weighted SAR with Distributed Gain 

Binary weighting can be achieved also by using equal DACs 

with a single reference voltage but with gain / scaling 

elements 

Due to scaling MSB DAC is most critical 

Linear transformation enables distributed gain 


192

Algorithmic Analog-to-Digital Converter 


Comparator threshold constant 

Voltage increment/decrement 

constant 

remainder is doubled in each 

iteration step 

accurate x2 circuit required 

193



194



195

Robertson Diagram 


196

Illustration in Robertson Diagram 

2. 3. 4. 


1. 

5. 

197


Long conversion time 

N cycles per inout sample 

ADC 

DAC 


198



199

Voltage Doubling in Algorithmic Converter 

V 1 

Sample remainder V err together with opamp offset voltage 

Amplifier configured as voltage follower 

C2 charged to amplifier offset voltage 


V 2 

200


V 1 

Disconnect input, discharge C 1 

Transfer charge of C 1 to C 2 


V 2 

201


Disconnect C2, charge Q2 unchanged 

Sample input again 

V 1 


V 2 

202


V 1 

Combine charge on C1, offset compensated, 

Four clock cycles required! 


V 2 

203

Weighted SAR with Distributed Gain 

Algorithmic converter in folded implementation 

Long conversion time 

N x TADC + N x TDAC 

Speed-up by insertion of ADC and S&H in each stage 

pipelining: high throughput at the price of latency 


204

Pipelined ADC 1 

Going for pipelined-ADC means 

– cut the feed-back loop 

– add a sample-and hold at the output of each stage to store 

the remainder, i.e. the stage quantization error 

– add a comparator, i.e. coarse ADC at input of each stage 


205

Pipelined ADC 2 


206

High-Speed ADC: Pipeline Processing 


207

Robertson Diagram with Threshold Error 


208

Impact of Comparator Offset on 

ADC Performance 


As soon as the residue leaves 

the convergence region the 

result suffers from major errors 

209

Impact of Comparator Offset on 

ADC Performance 

Comparator offset reflects in 

non-linearity of ADC characteristic 


210

Impairments in SAR Algorithms 

Finding: 

Each error in the amplifier gain or quantizer threshold causes 

divergence of the convergence algorithms and thus major 

conversion error 

How can we make SAR algorithms more robust 

Redundancy 

Redundant SAR algorithms 

Architecture implications 

Subranging ADC Pipeline ADC 


211

How can we Strengthen the Algorithm? 

Gain and offset errors shift the algorithm out of the 

convergence window. 

Does an additional threshold help? 

No, not necessarily. Important is that the residue is not 

scaled back fully. 


212

Redundant SAR Algorithms 

Stage quantizer with B bit 

(here B=2) 

Gain factor = 2 B 

Sensitive to thresh. var. 


Stage quantizer with B bit 

(here B=2) 

Gain factor < 2 B 

redundant SAR 

not sensitive to thres. var. 

213

Redundant Pipeline ADC Algorithm 

Redundant algorithm 

– Two thresholds 

– Gain ( = 2 ) does not scale 

residue back to full scale 

Stage resolution 1 bit 

Information contained 

in b i is 1.5 bit 

Redundancy 

Residue stays in 

convergence box even 

with strong gain and 

offset variations 


214

Subranging Principle 

quantization error 

Principle: Coarse quantization in frontend ADC and fine 

quantization of residue in backend ADC 

Pipelining possible (s&h between frontend and backend 

Generalization to multi-stage ADC ( pipeline ADC) 


215

Model of Frontend ADC 


216

Linear Model of Subranging ADC 


217

What is the “Digital Result Combiner“? 

Output of forward and backward ADC from last slide: 

Multiply result of backend ADC by 1/a and add to B out,1 

Overall quantization error only depends on quantization error 

of backend ADC 

Quantization error of backend ADC is scaled by 1/a 

Resolution: 


218

Linear Model of Subranging ADC 

Effective resolution of frontend ADC is ld(a) 

not necessarily the same as the number of bits of B out,1 

Analog and digital gain must match, otherwise leakage of 

quantization error of frontend ADC 


219

Reconstruction of Signal 

Error free reconstruction requires matching between analog 

gain a and digital gain a d 

In the context of variations this requires calibration 

matching 


220

General Pipeline SAR ADC 


221

General Pipeline SAR ADC II 

As long as analog and digitals gains match all intermediate 

terms vanish 

Resolution R: 

Gain elements determine resolution, not the stage quantizers 

Effective stage resolution: 

Last stage must not saturate under all circumstances! 


222

Background Calibration for Stage Gain 


Digital gain is 

continuously 

adjusted, i.e. even 

slow transient 

variations are 

corrected 

Li et al., Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy, TCAS II, 9/2003. 

Fu et al., A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters, JSSC, 12/1998 

Liu et al., A 15b 40MS/s CMOS Pipelined ADC with Digital Background Calibration, JSSC, 5/2005 

many more … 

223

Classification of Callibration Techniques 

Calibration comprises two phases 

– Error estimation 

– Error correction 

Analog approach additional analog components, noise, 

power, distortion, etc. 

Digital approach: Works on reults only, i.e. does not interfere 

with analog signal processing 

Calibration 

Foreground Background 


Virtual True 

Ginés et al., A Survey on Digital Background Calibration of ADCs, ECCTD, 2009. 

224

Summary Pipeline ADC 

Stage errors can be tolerated if the residue stays inside the 

convergence region 

– Minimum requirement is that the residue is back in the convergence region 

before the final quantizer) 

– Take care for nonlinearity which is not revealed by the linear model 

Trade-off sampling frequency – resolution – latency 

Number of stages, i.e. number of elements grows linearly 

with resolution (not exponentially, ref flash ADC) 

Accurate sample-and-hold elements required 

(That’s the reason why pipelined time-to-digital converters do not exist) 


225

Nyquist Rate Analog-to-Digital Converters 

– Flash Converter – 


226

implemented 

as parallel 

connection 

of 2 unit resistors 


Flash Converter 

Generate all switching thresholds in parallel 

and compare them to input voltage in parallel 

very fast, but high effort in terms of 

power, area, noise generation, clock 

distribution, input buffering 

high speed applications with moderate 

resolution 

227

Advantages 

Properties of Flash ADC 

– parallel processing very fast 

– no analog post-processing 

Disadvantages: 

– Huge hardware effort and power consumption (2 N ) 

– high input capacitance 

– synchronous routing of clock signal 

Good for high-speed converters with low # of bits 


228

thermometer code 

one-hot code 

transition detector 

Flash Converter 


Thermometer-to-binary 

decoder often 

implemented in 2 steps 

– thermo one-hot 

– one-hot binary 

Allows for insertion of 

bubble correction in 

between decoders 

229

Bubble Correction in Flash Converter 


230

Bubble Correction in Flash Converter 

Bubbles in flash converters: 

Source of bubbles: 

– noise 

– meta-stability 

– x-talk 

– mismatch 

– … 

0 0 0 0 0 0 1 1 1 1 1 1 

0 0 0 1 0 0 1 1 1 0 1 1 

Basic bubble correction with 3-input NAND gate: transition 

only detected if more than one high signal occurs. 

More complex encoders require to eliminate long distance 

errors 


231

Interpolating Flash Converter 


Preamp. with moderate 

gain to provide smooth 

transition region 

Latch for sign detection 

Resistive interpolation 

to create additional 

transition curves in 

between 2 regular ones 

232

Interpolating Flash Converter 


Interpolation does not work at 

boarders 

Overrange amplifiers required 

233

Interpolating Flash Converter (cont) 


additional series resistors to balance 

delays in high-speed interpolating 

flash converters 

234

Kickback Effect 

Especially in flash converters 

Clocked comparators produce lots of 

noise at their inputs when toggling 

from track to latch mode. 

Different impedance seen from both 

comp inputs 

(input drive vs. resistor ladder) 

Differential error that may corrupt 

next conversion 

Decay of error sets max sample rate 


235

Folding ADC 


Similar to flash ADC: 

Reuse comparators by 

folding voltage back to 

reference range 

Reduced number of 

latches, i.e. suitable for 

high-speed ADCs with 

med. resolution 

Folding blocks cause 

nonlinearity 

Increased frequency 

236

Folding ADC: Operation Principle 


Folding Blocks can be 

built by using several 

diffpairs connected to the 

same load resistors 

current is summed up 

and converted to the 

output voltage 

Frequency increases 

tough bandwidth 

requirements 

237

Folding ADC: Basic Schematic 


238

High-Speed ADC: Parallel Processing II 

Idea: 

Use N (slow) converters in 

parallel in a time multiplexed 

mode to achieve high-speed 

data conversion 

Effort: 

• N parallel converters 

• Sampler and mux at full-speed 


239

High-Speed ADC: Parallel Processing I 


240

Chapter 7 

Comparators 


241

Ideal Comparator 

Compare input signal to reference and provide binary output 

signal 

Often same symbol as for opamp 

(reasonable as open loop opamp behaves like a comparator) 

Comparator is essentially an amplifier with saturation, 

ideal comparator means infinite gain in VCVS not realistic 


242

Static Characteristics of Comparator 

Comparator gain 

Maximum voltage for negative saturation V DL 

Minimum voltage for positive saturation V DH 

Comparator resolution: (min. voltage increment, determines comparator gain) 

Offset voltage: Horizontal shift of characteristic 

Input common mode range 


243

Dynamic Characteristics of Comparator 

Note: 

Comparators work in large signal mode of operation 

– basic circuit theory to reveal trade-offs and mechanisms 

– simulation to determine actual performance figures 

Main dynamic performance figure: propagation delay td 


244

Operational Amplifier as Comparator 

Opamp in open-loop configuration is comparator 

– asynchronous 

– relatively slow due to high gain and stability requirement 

– offset error (may be compensated by correlated double sampling, 

but this also means synchronous operation) 

– Consider DC operating point at input for a reference voltage ≠ 0 

– Compensation cap may be disconnected during latching 


245

OpAmp Comparator Dynamics 

Gain-Bandwidth trade-off 

– gain determined by desired resolution 

– bandwidth determined by desired propagation delay 

Amplifier model 

Step response 

Propagation Delay 

(for min step, larger step is faster) 


output signal [norm] 

1 

0.9 

0.8 

0.7 

0.6 

0.5 

0.4 

0.3 

0.2 

0.1 

-2.0 -0.1 

-0.5 

Response of Stable 1st Order Linear System 

-1.0 

-1.0 

-0.5 

-2.0 

-0.1 

0 

0 2 4 6 8 10 

time [AU] 

246

Comparator Propagation Delay 

Linear mode of operation 

Propagation delay for small input signals is determined by 

linear small signal dynamics of amplifier 

Slew rate limited mode of operation 

Propagation delay for large input signals is dominated by 

slew rate of opamp output stage 

Propagation delay for slew rate limited operation 


247

Discrete Time Comparators 

In some applications comparator function only desired 

– during certain intervals 

– at certain discrete time instances 

Allows for offset compensation via auto-zeroing 

and other switched capacitor benefits 

Allows for amplifiers in positive feedback configuration 

– full level always reached 

– gain boosting (reuse one amplifier by cyclic amplification 


248

Track & Latch Circuit I 


249

Track & Latch Circuit II 


250

Principle of Track-and-Latch Stage 


251

Linear Dynamic of Latch 

Linear small signal analysis (ref. Schaltungstechnik 2) 

Node voltages 

Differential voltage 

Propagation delay 


output signal [norm] 

1 

0.9 

0.8 

0.7 

0.6 

0.5 

0.4 

0.3 

0.2 

0.1 

Response of Instable 1st Order Linear System (Latch) 

0.4 

0.1 

0.01 

0 

0 0.5 1 1.5 2 

time [AU] 

2.5 3 3.5 4 

252

Latched Comparators I 

Standard architecture for high-speed comparators 

Latch offset voltage limits resolution of latch-only comparator 

scaled down by gain of pre-amplifier 

Two step approach: 

– analog pre-amplifier stage(s) 

– regenerative track and latch stage 


253

Pre-amplifier: 

– 1-3 amplifier stages 

Latched Comparators II 

– low gain, high-speed 

– delay along amplifier chain 

– separation of input from latch to reduce loading and avoid 

kickback effect 


254

Track & latch circuit: 

Latched Comparators III 

– amplifies signal in track mode 

– restores (regenerates) signal to full rail in regenerative 

latch mode (positive feedback) 


255

Input Referred Offset of Latch 

Input referred offset error of latch stage is reduced by gain A 

of pre-amplifier 


256

Current Mode (CML) Latch 

Combines amplifier and 

latch functionality 


257

Memory and Hysteresis in Comparators 

Hysteresis: 

Switching threshold is different when switching from low to 

high and from high to low, respectively. 

Useful to avoid bouncing outputs for small (noisy) signals 

near comparator threshold 

Memory effect: 

Kind of hysteresis that causes the comparator decision to be 

dependent on previous decisions. 

Has to be strongly avoided in Nyquist rate ADCs such as 

flash converters. 


258

Elimination of Memory Effect 

Precharge and equalize circuit elements eliminate all 

information from previous cycles and decisions 


259

Switched Capacitor Comparator 

Offset compensated 

Threshold determined by capacitynce ratio 


260

Chapter 8 

Oversampled Converters 

Sigma-Delta Modulator 


261

Quantization Noise in A/D-Converters 


262

Linear Model of Quantization Noise 


263

Quantization Noise and Oversampling 


264



265



266

Feasibility of Oversampling 

Goal: Implement ADC (12bit, 44kHz BW) by 1 bit quantizer 

with oversampling 

12 bit 

Same SNR with 1 bit quantizer: 

Sampling frequency: 

Conclusion: Even medium resolution and low bandwidth 

leads to unacceptably high OSR 


267

Oversampling with Noise Shaping 


268

First Order Noise Shaping 


269



270



271

Calculation of Signal-to-Noise Ratio 


272



273



274

SC Implementation of 1. Order 

ΣΔ Modulator 


275

DAC Accuracy 

Linearity error of DAC looks like input signal 

DAC needs full accuracy even if quantizer resolution is low 

Dynamic element matching 

randomizes DAC linearity errors suppressed by OSR 


276

Comparison Nyquist Rate vs. SD AD 

Nyquist Rate ADCs Sigma Delta ADCs 

High voltage domain resolution Low voltage domain resolution 

in extreme case only 1 bit 

Low time domain resolution 

f s f Nyquist ( x 2-10) 

Low to medium resolution 

..(high) 


High time domain resolution 

f s >> f Nyquist ( x 64-512) 

Very high resolution 

up to 20 bit 

Result can be directly used Large decimation filter required 

One output symbol = one sample One sample distributed over many 

output symbols 

Medium speed requirements for all 

circuit block 

Very high speed requirements for 

OpAmps, DAC, etc. 

277

2. Order Noise Shaping 


278

Calculation of Transfer Functions 


279

Noisespectrum 


280

Simulation with Matlab/Simulink 


281

Simulation for OSR=32 


282

Output Spectrum of ΣΔ-Modulator for 

Sinusoidal Input Signal 


283

Output Spectrum of ΣΔ-Modulator for 

Sinusoidal Input Signal 


284

Input Level Dependent SNR 

2. Order 


1. Order 

285

OSR Dependent Peak-SNR 


286

Tones 


287

power spectral density 

0 

-50 

-100 

Tones in Frequency Domain 

-150 

0 0.1 0.2 0.3 0.4 0.5 

frequency/sampling frequency 


288

Dithering 

Reduce the risk of tones by randomizing (artificially) the 

comparator input signal: Dithering 


pseudo random signal 

affected by noise shaping, i.e. 

noise power mainly shifted to high frequencies 

SNR only slightly reduced 

289



0 

-50 

-100 

-150 

0 0.1 0.2 0.3 0.4 0.5 


0 

-50 

-100 

-150 

0 0.1 0.2 0.3 0.4 0.5 


-100 




0 

-50 

-150 

0 0.1 0.2 0.3 0.4 0.5 


0 

-50 

-100 

-150 

0 0.1 0.2 0.3 0.4 0.5 


290

maximum noise peak 

Tones 

input DC level 


291

3. Order Single-Loop ΣΔ-Modulator 

(not cascaded) 

Deviation from „ideal“ transfer functions due to stability 

requirements 


J. Sauerbrey 

292

STF of 3. Order ΣΔ-Modulator 


293

Noiseshaping of Various ΣΔ-Modulators 


294

Cascaded ΣΔ-Modulator (Multi stAge noise Shaping) 


295

Noiseshaping of Various ΣΔ-Modulators 


296

3. Order MASH Structure 


297

Scaling of ΣΔ-Modulator 

1. If inputs of integrators become too large for a significant time 

the integrators saturate 

non-linearity clipping strong non-linear distortion 

(Comparator should be only non-linear component) 

2. Exploit full dynamic range for good SNR 

Modulator Scaling: 

Linear transformation so that 

saturation of integrators is avoided 

dynamic range is exploited 


298

hist(S1) 

12000 

10000 

8000 

6000 

4000 

2000 

0 

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 

S1 


hist(S2) 

9000 

8000 

7000 

6000 

5000 

4000 

3000 

2000 

1000 

0 

-4 -3 -2 -1 0 1 2 3 4 

S2 

299

hist(S1) 

x 10 

2.5 

2 

1.5 

1 

0.5 

0 

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 

S1 


hist(S2) 

1.8 

1.6 

1.4 

1.2 

1 

0.8 

0.6 

0.4 

0.2 

x 10 

2 

0 

-1.5 -1 -0.5 0 0.5 1 1.5 

S2 

300

hist(S1) 

2.5 

2 

1.5 

1 

0.5 

0 

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 

S1 


hist(S2) 

2 

1.8 

1.6 

1.4 

1.2 

1 

0.8 

0.6 

0.4 

0.2 

0 

-1.5 -1 -0.5 0 0.5 1 1.5 

S2 

301

Application of ΣΔ-Modulator 

in Data Converters (ADC) 


302

ΣΔ-Analog-to-Digital Conversion 


303

Decimation Filtering 


304

Sinc-Filter 

Basic low-pass filter averages N subsequent samples: 

Stephan Henzler Mixed-Signal-Electronics 2012/13 305

Sinc Filter Transfer Functions 


306

Sinc Filter Transfer Functions 


307

Sinc Filter Implementation 


308

Implementation of Sinc-Filter 


309

ΣΔ-Digital-to-Analog Conversion 


310

ΣΔ-Digital-to-Analog Conversion 


311

Multi-Bit Sigma Delta Converter 

Replace single-bit quantizer by multi-bit quantizer 

Quantizer: Comparator Flash ADC 

Feedback DAC: implicit real DAC 

Comparator and DAC nonlinearity become critical 

Countermeasures: Dynamic element matching, mismatch 

shaping, trimming, (digital) correction 

Benefit: Reduced OSR and/or better resolution 


312

Continuous Time Sigma-Delta Converter 


313

Comparison of Discrete- and Continuous 

Time Sigma-Delta Converters 

Anti-Aliasing Filter Explicit anti-aliasing filter 

(AAF) required 

Sampling Sampling at input 

low jitter & full linearity 

required for sampler 

Max. frequency and 

bandwidth of opamps 

Discrete-Time Continuous-Time 

All transients must settle 

within half of clock cycle, 

quickly changing pulses 

everywhere in circuit 

high bandwidth 

requirements limit max. 

frequency 


Implicit filtering 

AAF may be obsolete for 

some applications 

Sampling at comparator, i.e. 

within ∑∆-loop 

sampling error subject to 

noise shaping 

Continuous time waveforms 

5-10x relaxed bandwidth 

requirements 

higher clock frequency 

possible 

314



Jitter Only critical for sampler but 

not for rest of sigma delta 

modulator 



Very sensitive to timing 

variations of clock 

Loopdelay Not an issue Very sensitive to loop delay 

Switches Signal dependant on 

resistance 

Signal dependant 

comparator delay 

No switches 

Not an issue Very sensitive causes 

harmonic distortion 

315



Feedback-DAC Low sensitivity to waveform 

settling not critical 

Process variations Filter transfer function 

based on capacitor ratios 

very robust 



Very sensitive to waveform 

and settling, limits linearity 

of modulator 

Filter transfer function 

depends on RC constants, 

i.e. very sensitive to 

variations 

Noise generation Switching generates noise Reduced supply and ground 

noise 

316

Web References 

Murmann. VLSI Data Conversion Circuits. Stanford University. 

Henzler. High-Speed Digital CMOS Circuits. TU Munich. 


317

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