Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 86
IN T ER :: Block → Bool
IN T ER block bid d1 . . . dn ∼ r { τ1 id1 . . . τp idp. stmts } =
∀d1 . . . dn r. S ∅stmts ⇒ SIN T ER ′ ∅ stmts
SIN T ER ′ φ :: StmtListStmtList → Bool
SIN T ER ′ φ stmt1 . . . stmtn =
let c1 = SIN T ERφstmt1 in
let c2 = SIN T ERφ∪{stmt1}stmt2 in
.
let cn = SIN T ER φ∪{stmt1,...,stmtn−1}stmtn in
c1 ∧ . . . ∧ cn
SIN T ERφ :: StmtList → Stmt → Bool
SIN T ERφ assert e str = True
SIN T ERφ e1 = e2 = True
SIN T ERφ if e { stmts1 } else { stmts2 } =
if e then SIN T ER ′ φstmts1 else SIN T ER ′ φstmts2 SIN T ERφ for i = e1..e2 { stmts } =
∀ i. e1 ≤ i ≤ e2 −→ SIN T ER ′ φstmts ∧
∀ i j. e1 ≤ i ≤ e2 ∧ e1 ≤ j ≤ e2 ∧ i = j −→ SIN T ER ′ {i↦→j}stmtsstmts
SIN T ERφ a ; blkinst ; b at (x1, y1) =
let (x2, y2) = (x1 + Width(a ; blkinst ; b), y1 + Height(a ; blkinst ; b)) in
IN T ERSECT ′ (x1,y1),(x2,y2)φ
IN T ERSECT ′ (x1,y1),(x2,y2) :: ((Exp × Exp) × (Exp × Exp)) → StmtList → Bool
IN T ERSECT ′ (x1,y1),(x2,y2) stmt1 . . . stmtn =
let c1 = IN T ERSECT (x1,y1),(x2,y2)stmt1 in
.
.
let cn = IN T ERSECT (x1,y1),(x2,y2)stmtn in
c1 ∧ . . . ∧ cn
IN T ERSECT (x1,y1),(x2,y2) :: ((Exp × Exp) × (Exp × Exp)) → Stmt → Bool
IN T ERSECT (x1,y1),(x2,y2) assert e str = True
IN T ERSECT (x1,y1),(x2,y2) e1 = e2 = True
IN T ERSECT (x1,y1),(x2,y2) if e { stmts1 } else { stmts2 } =
if e then IN T ERSECT (x1,y1),(x2,y2)stmts1
else IN T ERSECT (x1,y1),(x2,y2)stmts2
IN T ERSECT (x1,y1),(x2,y2) for i = e1..e2 { stmts } =
∀ i. e1 ≤ i ≤ e2 −→ IN T ERSECT (x1,y1),(x2,y2)stmts
IN T ERSECT (x1,y1),(x2,y2) a ; blkinst ; b at (x ′ 1, y ′ 1) =
let (x ′ 2 , y′ 2 ) = (x′ 1 + Width(a ; blkinst ; b), y′ 1 + Height(a ; blkinst ; b)) in
(x ′ 2 ≤ x1) ∨ (x2 ≤ x ′ 1 ) ∨ (y′ 2 ≤ y′ 1 ) ∨ (y2 ≤ y ′ 1 )
Figure 4.11: Generating intersection theorems