Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 82
SB ′ :: BlockEnv → Block → (SizeFunc × SizeFunc)
SB ′ β block bid d1 . . . dn ∼ r attributes { height = h. width = w. } { τ1 id1 . . . τp idp.
stmts } =
let m = S ′ βstmts in
(λd1 . . .dn r. let (id1, . . . , idp) = (ι(id1, . . .,idp). m) in w,
λd1 . . . dn r. let (id1, . . . , idp) = (ι(id1, . . . , idp). m) in h)
Figure 4.9: Converting Quartz size expressions into QuartzLayout size functions
automatic. Figure 4.8 gives the definition of the function Bβ which gives the semantics of a
block as a logical predicate. This function gives Quartz a formal semantics in HOL, using an
environment β which maps block identifiers to their definitions.
The function in Figure 4.8 is implemented in the Quartz compiler layout processing module.
The only difference between the formal definition and the compiler implementation is that the
function B ′ β is not executed, instead the modelling of block instantiation within QuartzLayout
(Section 4.4.2) is used. For example, the semantics of the map n R combinator, as generated
by the compiler, are described by:
λ(n, R)io. ∀j. (0 ≤ j ∧ j ≤ n − 1) −→ B ′ βR(i[j], o[j])
In Isabelle’s ASCII syntax this is written as (note that “o” has been replaced with “o ” since
“o” is a reserved keyword in Isabelle/HOL):
% (n, R) i o . ALL (j::int). ((0