Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 81
B ′ β :: BlockEnv → Blkinst → Predicate
B ′ β bid p1 . . . pn =
if bid ∈ β then Bββ(bid)(p1, . . .,pn)
else bid(p1, . . .,pn)
B ′ β [ b1 , . . ., bn ] =
let m1 = B ′ βb1 in
.
let mn = B ′ β bn in
λ(x1, . . . , xn) (y1, . . .,yn). m1(x1, y1) ∧ . . . ∧ mn(xn, yn)
B ′ β b1 ; b2 =
let m1 = B ′ β b1 in
let m2 = B ′ β b2 in
λxy. ∃s. m1(x, s) ∧ m2(s, y)
B :: BlockEnv → Block → Predicate
Bβ block bid d1 . . . dn ∼ r { τ1 id1 . . . τp idp. stmts } =
λd1 . . . dn r. ∃ id1 . . .idp. S ′ β stmts
S ′ :: BlockEnv → StmtList → Bool
S ′ β stmt1 . . . stmtn =
let m1 = Sβstmt1 in
.
let mn = Sβstmtn in
m1 ∧ . . . ∧ mn
Sβ :: BlockEnv → Stmt → Bool
Sβ assert e str = e
Sβ e1 = e2 = e1 = e2
Sβ if e { stmts1 } else { stmts2 } =
let m1 = S ′ βstmts1 in
let m2 = S ′ βstmts2 in
if e then m1 else m2
Sβ for i = e1..e2 { stmts } =
∀i. e1 ≤ i ≤ e2 −→ S ′ βstmts Sβ a ; blkinst ; b at (x, y) = B ′ βblkinst(a, b)
Figure 4.8: Converting Quartz blocks into their semantic interpretation in Higher-Order
Logic. The function Bβ defines the formal semantics of Quartz using HOL.