Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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TABLE OF CONTENTS vii 7 Conclusion and Future Work 164 7.1 This Thesis’ Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.3 Comparison with Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.3.1 VHDL with Explicit Co-ordinates . . . . . . . . . . . . . . . . . . . . 168 7.3.2 Relative Placement in Pebble . . . . . . . . . . . . . . . . . . . . . . . 168 7.3.3 Ruby and Lava . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.4 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.4.1 Further Support For Alternative Layout Interpretations . . . . . . . . 171 7.4.2 Less User Interaction In Proofs . . . . . . . . . . . . . . . . . . . . . . 172 7.4.3 Integrating Layout and Functional Verification . . . . . . . . . . . . . 173 7.4.4 Run-time Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.4.5 Properties of N-Dimensional Combinators . . . . . . . . . . . . . . . . 174 Bibliography 175 A Quartz Language Grammar 184 B Theoretical Basis for Layout Reasoning 187 B.1 IntAlgebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 B.2 Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 B.3 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 B.4 Inbuilt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 B.5 SeriesComposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 B.6 ParallelComposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 B.7 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 B.8 Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 B.9 CompilerSimps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 B.10 QuartzLayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 B.11 Minf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 C Placed Combinator Libraries 207 C.1 Prelude Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
TABLE OF CONTENTS viii C.1.1 fst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 C.1.2 R −1 (converse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 C.1.3 R n (rcomp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 C.1.4 Q\P (conjugate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 C.1.5 map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 C.1.6 (tri) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 C.1.7 R↔S (beside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 C.1.8 row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 C.1.9 grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 C.1.10 loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 C.2 Recursive Index Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 C.2.1 ichain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 C.2.2 imap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 C.2.3 irow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 C.2.4 irdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 C.2.5 igrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 C.3 Irregular Grid Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 C.4 Square Element Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.5 H-Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 D Circuit Layout Case Studies 268 D.1 Median Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 D.1.1 Quartz Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 D.1.2 Theory max2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 D.1.3 Theory min2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 D.1.4 Theory eq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 D.1.5 Theory insert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 D.1.6 Theory lct cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 D.1.7 Theory locater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 D.1.8 Theory del cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 D.1.9 Theory compactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 D.1.10 Theory insert median . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Page 1 and 2: Imperial College of Science, Techno
Page 3 and 4: Acknowledgements Firstly, I’d lik
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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Appendix C Placed Combinator Librar
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