Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 79
Theorem 17 ∀ b t f. (∀y. 0 ≤ f y) ⇒ 0 ≤ sum(b, t, f)
We also prove theorems about the inter-relationship between these two functions, such as:
Theorem 18 ∀ b t f. (∀ x. 0 ≤ fx) ⇒ maxf(b, t, λk. sum(b, k, f)) = sum(b, t, f)
Theorem 19
∀ b t f. b ≤ t ∧ (∀ x. 0 ≤ f x) ⇒
maxf(b, t + 1, λk. sum(b, k, f)) = maxf(b, t, λk. sum(b, k, f) + f(t + 1))
Proofs of all these theorems and many others about maxf and sum are listed in Appendix B.7.
4.5 Generating Theories of Quartz Programs
Given that we are using a shallow embedding of Quartz in Isabelle/HOL, we can not reason
about Quartz descriptions directly. Instead, we must translate Quartz descriptions into
semantic descriptions in Higher-Order Logic.
4.5.1 Compiler Architecture
When in verification mode the Quartz compiler translates from Quartz descriptions to Is-
abelle/HOL during compilation. This allows the Quartz compiler to resolve all overloading
prior to generating HOL descriptions - t a vital step since our QuartzLayout system does not
support overloading.
Figure 4.7 shows the functionality of the Quartz compiler when in layout verification mode.
Layout verification is divided between the Layout Processing and Isabelle modules. The
Layout Processing module converts Quartz programs into their HOL semantic definitions
and generates theorems that must be proved to verify the correctness of a layout. These
HOL definitions and proof obligations are generated in an abstract data format which is then
passed to the Isabelle module.