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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 72<br />

CompilerSimps<br />

Structures<br />

Functions<br />

ParallelComposition<br />

IntAlgebra<br />

Quartz<strong>Layout</strong><br />

SeriesComposition<br />

Inbuilt<br />

Block<br />

Types<br />

Figure 4.3: The Quartz<strong>Layout</strong> theory hierarchy. Rectangular nodes develop the theory <strong>of</strong> the<br />

language itself, oval nodes define functions for size expressions and useful theorems. Arrows<br />

indicate dependencies.<br />

actual hardware generated by a Quartz description is <strong>of</strong> interest only so far as it affects the<br />

layout <strong>of</strong> the design and wiring is <strong>of</strong> no interest, since we assume that wiring resources are<br />

separate from computational resources.<br />

Our Quartz model is built up hierarchically from a number <strong>of</strong> Isabelle theories, as illustrated<br />

in Figure 4.3. In this chapter we describe how some <strong>of</strong> the language features <strong>of</strong> Quartz are<br />

modelled and identify some useful theorems. The full Isabelle theory development can be<br />

seen in Appendix B.<br />

4.4.1 Type System<br />

Isabelle/HOL has types and polymorphism based on the Hindley/Milner system [53] - the<br />

same basic system as Quartz. It also supports overloading, although it is based on type<br />

classes [84] which are not compatible <strong>with</strong> the Quartz overloading system [64]. Overloading<br />

complicates verification since it is not necessarily possible to determine which block instance<br />

is selected and different instances can have different size expressions.<br />

In the Quartz<strong>Layout</strong> system we ignore overloading and assume it has been resolved prior to

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