Verification of Parameterised FPGA Circuit Descriptions with Layout ...

More documents

Recommendations

Info

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 70 (x21, y21) (x21, y21) (x11, y11) (x22, y22) (x11, y11) (a) x22 ≤ x11 (x22, y22) (x12, y12) (c) y12 ≤ y21 (x12, y12) (x11, y11) (x11, y11) (x21, y21) (x12, y12) (x21, y21) (b) x12 ≤ x21 (x12, y12) (x22, y22) (d) y22 ≤ y11 (x22, y22) Figure 4.2: Situations under which two rectangles will not overlap possibly being allocated to both. This must obviously be avoided in correct circuit descriptions. Ensuring this correctness criteria is the common target of work on relative placement. The problem of ensuring non-overlapping of n rectangles is a well understood objective in constraint programming [1, 6] and is a problem in placement algorithms, however in our case we are interested not in finding a solution to the problem but rather in checking one. Exist- ing work on constraint solving applied to this problem is not suitable for adaptation to the Quartz system because we permit a much ricer language of expressions than simple arithmetic operations to define block sizes. Two objects placed on a n-dimensional surface will not overlap if is one dimension in which they can not intersect. For rectangles on a two-dimensional surface this means that one block must be either below or above the other, or to the left or right of it. This means that there are four possible situations in which a layout can be correct, illustrated graphically in Figure 4.2. When the rectangle A is described by corners (x11, y11) and (x12, y12), and rectangle B is described by corners (x21, y21) and (x22, y22) this can be represented by the logical disjunction: (x22 ≤ x11) ∨ (x12 ≤ x21) ∨ (y12 ≤ y21) ∨ (y22 ≤ y11)
CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 71 This leads naturally to the definition of intersection correctness: Definition 7 For every pair of block instantiations A and B within a block, where A is placed at (xA, yA) with size functions (widthA, heightA) and B is placed at (xB, yB) with size functions (widthB, heightB), for all possible allowable input values: (xB +widthB ≤ xA) ∨ (xA+widthA ≤ xB) ∨ (yB+heightB ≤ yA) ∨ (yA+heightA ≤ yB) A naive implementation of Definition 7 has (n − 1) × (n − 2) proof obligations. However, by exploiting symmetry this can be reduced to (n − 1) × (n − 2)/2 obligations. This still means that for blocks with a large number of components instantiated within them a large number of proof obligations are generated, however because Quartz designs tend to be broken up into many entities each of which only contains a few constructs this is less of a problem than it might seem at first. The generation of proof obligations from Quartz descriptions is discussed in detail in Section 4.5, however it is worth mentioning here the special case of iteration. A Quartz for loop can lead to more than one block being instantiated which can potentially intersect with one another. When generating proof obligations for a for loop construct, an additional proof obligation therefore exists that for any two iterations of the loop, any instantiated blocks can not overlap with one another. 4.4 Proof Environment We develop a mechanised theorem proving environment for layout verification based on a shallow embedding [8] of Quartz in Higher-Order Logic. This involves the definition of the semantics of Quartz constructs in terms of HOL connectives. We develop the QuartzLayout library of theories which provides definitions for and useful theorems about a sufficient subset of Quartz to enable layout proofs. Our embedding is quite different to the typical embeddings of hardware description languages in logic since our aim is not to engage in functional verification but rather to verify layout. This means that the
Page 1 and 2:
Imperial College of Science, Techno
Page 3 and 4:
Acknowledgements Firstly, I’d lik
Page 5 and 6:
TABLE OF CONTENTS iv 2.5 Isabelle:
Page 7 and 8:
TABLE OF CONTENTS vi 5.3.1 Speciali
Page 9 and 10:
TABLE OF CONTENTS viii C.1.1 fst .
Page 11 and 12:
Chapter 1 Introduction This thesis
Page 13 and 14:
CHAPTER 1. INTRODUCTION 3 B A C Fig
Page 15 and 16:
CHAPTER 1. INTRODUCTION 5 pler, all
Page 17 and 18:
CHAPTER 2. BACKGROUND AND RELATED W
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
Page 27 and 28:
Page 29 and 30: CHAPTER 2. BACKGROUND AND RELATED W
Page 45 and 46: CHAPTER 3. GENERATING PARAMETERISED
Page 75 and 76: Chapter 4 Verifying Circuit Layouts
Page 77 and 78: CHAPTER 4. VERIFYING CIRCUIT LAYOUT
Page 79: CHAPTER 4. VERIFYING CIRCUIT LAYOUT
Page 117 and 118: Chapter 5 Specialisation In this ch
Page 119 and 120: CHAPTER 5. SPECIALISATION 109 opera
Page 121 and 122: CHAPTER 5. SPECIALISATION 111 // Ha
Page 123 and 124: CHAPTER 5. SPECIALISATION 113 circu
Page 125 and 126: CHAPTER 5. SPECIALISATION 115 const
Page 127 and 128: CHAPTER 5. SPECIALISATION 117 block
Page 129 and 130: CHAPTER 5. SPECIALISATION 119 Modif
Page 131 and 132:
CHAPTER 5. SPECIALISATION 121 Buffe
Page 133 and 134:
CHAPTER 5. SPECIALISATION 123 a fas
Page 135 and 136:
CHAPTER 5. SPECIALISATION 125 block
Page 137 and 138:
CHAPTER 5. SPECIALISATION 127 y y y
Page 139 and 140:
CHAPTER 5. SPECIALISATION 129 with
Page 141 and 142:
CHAPTER 6. LAYOUT CASE STUDIES 131
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
CHAPTER 7. CONCLUSION AND FUTURE WO
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Bibliography [1] A. Aggoun and N. B
Page 187 and 188:
BIBLIOGRAPHY 177 [19] H. Gelernter.
Page 189 and 190:
BIBLIOGRAPHY 179 [41] Y. Li and M.
Page 191 and 192:
BIBLIOGRAPHY 181 [60] L. C. Paulson
Page 193 and 194:
BIBLIOGRAPHY 183 [83] J. Voeten. On
Page 195 and 196:
APPENDIX A. QUARTZ LANGUAGE GRAMMAR
Page 197 and 198:
Appendix B Theoretical Basis for La
Page 199 and 200:
APPENDIX B. THEORETICAL BASIS FOR L
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Appendix C Placed Combinator Librar
Page 219 and 220:
APPENDIX C. PLACED COMBINATOR LIBRA
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
Page 249 and 250:
Page 251 and 252:
Page 253 and 254:
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Page 265 and 266:
Page 267 and 268:
Page 269 and 270:
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
APPENDIX D. CIRCUIT LAYOUT CASE STU
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
Page 315 and 316:
Page 317 and 318:
Page 319 and 320:
Page 321 and 322:
Page 323 and 324:
Page 325 and 326:
Page 327:
show all

Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Create successful ePaper yourself

Delete template?

Save as template?