Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 69
A
B
C
E
D
(a) Incorrect containment
F
B
C
A
E
D
(b) Correct containment
Figure 4.1: Different layouts for the same components can affect containment within an area
meet. A block meets the containment requirement if all sub-blocks are instantiated within
the bounding box.
Definition 6 A block is correctly contained if, for all allowable values of all input variables
to the block, all instantiated sub-components fall within the block’s bounding box
∀x1, . . .,xn. assertions(x1, . . .,xn) ⇒ ∀(p ; B ; q at (x, y)) ∈ InstantiatedBlocks.
0 ≤ x ∧ 0 ≤ y ∧
x + Bwidth ≤ width(x1, . . . , xn) ∧ y + Bheight ≤ height(x1, . . . , xn)
Figure 4.1 illustrates how the same components can be laid out within a block in ways that
either fail or meet this layout correctness constraint.
The containment constraint is also vital for layout verification proofs. It permits hierarchical
proofs where the internal arrangement of blocks can be ignored and the block analysed purely
in terms of its size expressions. It is sometimes desirable to relax this correctness requirement,
as we discuss later in this chapter.
4.3.3 Intersection
The most significant area for potential problems with explicitly laid-out designs to arise is
in the intersection of blocks. While this problem is somewhat reduced by hierarchical design
descriptions and relative co-ordinates the possibility of errors is not totally eliminated. In-
tersection occurs when the bounding boxes of two blocks overlap, leading to logic resources
F