Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 68
4.3 Specifying Correctness
In order to formally verify anything it is necessary to state the requirements for correctness.
In the case of circuit layouts we define correctness in terms of validity, containment and
intersection.
4.3.1 Validity
Validity is a property of the size expressions (height and width) for a block:
Definition 5 A block size expression is valid if, for all allowable values of all variables in
the expression, it always evaluates to a value greater than or equal to zero.
∀x1, x2, . . . , xn. assertions(x1, x2, . . .,xn) ⇒ 0 ≤ f(x1, x2, . . . , xn)
This requirement may appear trivial and indeed its proof is often easy, however it is an
extremely important requirement. Blocks with size expressions that evaluate to negative
values will usually render otherwise correct layouts useless. A common proof obligation for
other correctness requirements is of the form:
sizeA ≤ sizeA + sizeB
This is provable only if it can be assumed that sizeB ≥ 0.
The implication in Definition 5 is also significant. It states that it is only necessary for size
expressions to be valid for inputs that meet the preconditions specified in the design (via
assertions). For example, a size expression n × 2 is valid provided that n ≥ 0.
4.3.2 Containment
The size of a block is a bounding box defined as a rectangle with bottom left co-ordinates (0, 0)
and the top right corner with co-ordinates as defined by the block’s size expressions. The size
of a block can be specified manually and can be regarded as a specification that a block must