Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Chapter 4
Verifying Circuit Layouts
In this chapter we describe how Quartz circuit layouts can be verified mechanically. Sec-
tion 4.1 introduces our basic approach and Section 4.2 explains why Higher-Order Logic was
selected as an good formalism. Section 4.3 discusses how we will define “correctness” of a lay-
out. Section 4.4 describes the theoretical developments that provide a proof environment for
Quartz layouts, while Section 4.5 describes how the Quartz compiler is adapted to generate
definitions and proof obligations automatically. Section 4.6 demonstrates the application of
our verification framework to the Prelude library and describes how automatically-generated
scripts are honed based on these examples, while in Section 4.7 we apply the system to a
range of other combinators. Section 4.8 discusses the strengths and weaknesses of our system
and Section 4.9 summarises this chapter.
4.1 Introduction
Using explicit co-ordinates to define the placement of components in parameterised circuit
descriptions can be complex and error-prone. The Quartz layout system based on giving
layout interpretations to higher-order combinators substantially reduces the scope for errors
since the task of describing a circuit layout is divided hierarchically into smaller and simpler
components. Combinators with layout interpretations can be written once and used many
times, so while the placement co-ordinates within each combinator are relatively simple, it is
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