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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 63<br />

function max(a : integer ; b : integer ) return integer is<br />

begin<br />

if a > b then<br />

return a ;<br />

else<br />

return b ;<br />

end if ;<br />

end function max;<br />

Figure 3.18: VHDL max function<br />

template can be parameterised in its upper and lower bounds and thus only one function<br />

needs to be generated for each usage <strong>of</strong> sum over the same function. The semantics <strong>of</strong> this<br />

VHDL sum function are the same as those <strong>of</strong> the Quartz/LE-Pebble function. If the range<br />

<strong>of</strong> the sum is zero then the default value <strong>of</strong> a (0) is returned, otherwise the sum is returned.<br />

An equivalent template can be instantiated for maxf. The n-input Quartz/LE-Pebble max<br />

function can be transformed to use nested calls to a 2-input VHDL max function defined as<br />

in Figure 3.18. Conditional expressions can be implemented using VHDL conditionals.<br />

Placement co-ordinates themselves are compiled into the appropriate constructs for a partic-<br />

ular target architecture, as specified by a directive in the source file. We have implemented<br />

placement support for the Xilinx Virtex and Virtex-II architectures, generating RLOC place-<br />

ment macros. Virtex and Virtex-II use different co-ordinate schemes and the Pebble compiler<br />

maps from the basic abstract grid onto these co-ordinate schemes.<br />

For the Virtex-II architecture, for example (see Chapter 2), each slice contains two look-up<br />

tables and other logic that can be explicitly instantiated. However placement co-ordinates<br />

are described in terms <strong>of</strong> individual slices. When mapping from Pebble to VHDL the grid is<br />

squashed so each set <strong>of</strong> two vertically adjacent 1 × 1 blocks are placed in the same slice. The<br />

basic layout element is thus a half-slice.<br />

3.9 Summary and Comparison <strong>with</strong> Related Work<br />

In this chapter we have described a layout infrastructure for the Quartz language which allows<br />

designers to apply explicit absolute or relative placement information to hardware designs.<br />

Our infrastructure allows Quartz higher-order combinators to be given layout interpretations

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