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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 62<br />

function sum template(b : integer ; t : integer ) return integer is<br />

constant b : integer := 0;<br />

variable a : integer := 0;<br />

variable n : integer ;<br />

begin<br />

for n in b to t loop<br />

a := + a ;<br />

end loop ;<br />

return a ;<br />

end function sum width ;<br />

Figure 3.17: VHDL template for implementing the LE-Pebble sum function<br />

Pro<strong>of</strong> By induction on n and re-arrangement using established properties <strong>of</strong> maxf and sum.<br />

Appendix B.9 gives mechanised pro<strong>of</strong>s for these simplification rules.<br />

Conditionals can sometimes be further simplified by taking advantage <strong>of</strong> the context specified<br />

by assertions <strong>with</strong>in blocks. For example, if a block contains an assertion which states m ≤ n<br />

then the correct branch <strong>of</strong> an if expression dependent on that condition can be selected<br />

statically. Alternatively, another common situation is for m = 0 and n ≥ 1 to be asserted,<br />

which can also be used to simplify the same expression.<br />

3.8 Compiling LE-Pebble into VHDL<br />

To complete the process <strong>of</strong> generating parameterised hardware libraries in an industry-<br />

standard format, LE-Pebble can be compiled into VHDL. The compilation <strong>of</strong> standard Pebble<br />

into parameterised structural VHDL has been reported previously [46, 48] however the addi-<br />

tion <strong>of</strong> new expression types that are not supported in VHDL to Pebble makes this process<br />

slightly more complicated.<br />

While VHDL does not support higher-order functions, it does support the definition <strong>of</strong> func-<br />

tions <strong>with</strong>in structural hardware descriptions. This mechanism can be used to compile com-<br />

plex functions in LE-Pebble such as maxf into VHDL by generating functions based around<br />

simple templates. Iterative version <strong>of</strong> sum and maxf are preferable for VHDL implemen-<br />

tation and these can be described equivalent to the recursive definitions <strong>of</strong> these functions.<br />

Figure 3.17 gives the VHDL template for the sum function. This can be instantiated for any<br />

particular function by replacing the text “” <strong>with</strong> the expression to evaluate. This

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