Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 60
which can not be further simplified of:
height = if(n = 0, 0, height(i[0] ; R ; o[0]) + height(i[n − 1..1] ; map n−1 R ; o[n − 1..1]))
width = if(n = 0, 0, max(width(i[0] ; R ; o[0]), width(i[n − 1..1] ; map n−1 R ; o[n − 1..1]))
Without knowing the value of n it is not possible to compile away the height() and width()
references in the same way as for iterative size expressions. One strategy for dealing with
these expressions is to mark them as requiring unwinding in the final output, in which case the
full expression can be evaluated at compile time and non-parameterised Pebble is generated 2 .
Another way for dealing with these expressions while maintaining parameterisation is to
compile the recursion directly into Pebble. This requires the addition of a fix operator to
Pebble expressions and makes them much more complex. This does resolve the issue and the
recursive Pebble expressions can be compiled into specific VHDL functions for translation
into VHDL (see the next section) however it does introduce unwanted complexity into Pebble.
An alternative, which is not a fully general approach, is to attempt to compute the transitive
closure of the recursive size functions. Often recursive blocks are controlled by a single
integer parameter which decreases by 1 for each recursive call and in these circumstances the
resulting value can often be determined. This approach depends on the complexity of the
height and width functions for the R block, however if the size of R is constant for all inputs
then the recursive functions can be simplified to just:
height = heightR × n
width = widthR
In general it is better to write iterative descriptions where possible as these can usually be
compiled more efficiently anyway.
2 This is the approach taken in the current implementation of the compiler.