Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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TABLE OF CONTENTS v 4.2 Choice of Formalism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3 Specifying Correctness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.1 Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.2 Containment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.3 Intersection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.4 Proof Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.4.1 Type System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4.2 Blocks and Block Instantiation . . . . . . . . . . . . . . . . . . . . . . 73 4.4.3 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5 Generating Theories of Quartz Programs . . . . . . . . . . . . . . . . . . . . . 79 4.5.1 Compiler Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.2 Generating Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5.3 Generating Proof Obligations . . . . . . . . . . . . . . . . . . . . . . . 83 4.6 Proving the Prelude Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.1 Proofs with Tacticals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.2 Improved Proof Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.6.3 Building a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.7 Proving Other Combinators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.7.1 Index Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.7.2 An Irregular Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.7.3 H-Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.7.4 Surround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.8 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5 Specialisation 107 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.2 Distributed Specialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.2.1 Specialising Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.2.2 Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.2.3 Verifying Distributed Specialisation . . . . . . . . . . . . . . . . . . . 114 5.3 Optimal Distributed Specialisation . . . . . . . . . . . . . . . . . . . . . . . . 116
TABLE OF CONTENTS vi 5.3.1 Specialising a Ripple Adder . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3.2 Modified Type System . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.4 High Level Specialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.5 Specialising a Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.5.1 Parallel Multiplier Implementation . . . . . . . . . . . . . . . . . . . . 122 5.5.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6 Layout Case Studies 130 6.1 Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.2 Adder Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.2.1 Ripple Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.2.2 Possible Tree Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.2.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3 Median Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.4 Butterfly Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.4.1 Butterfly Combinator . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.4.2 Implementing a bitonic merger . . . . . . . . . . . . . . . . . . . . . . 145 6.4.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.5 Binomial Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.5.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.5.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.6 Matrix Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.6.1 A 3D “cube” Combinator . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.6.2 Describing N-dimensional Combinators . . . . . . . . . . . . . . . . . 155 6.6.3 A 3D Matrix Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.6.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.7 Evaluation and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Page 1 and 2: Imperial College of Science, Techno
Page 3 and 4: Acknowledgements Firstly, I’d lik
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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