Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 58 The block size inference procedure ensures that all blocks are annotated with height and width expressions. If these expressions have been specified manually then no action is necessary, however if not the procedure executes the function SB to generate size expressions for the block. The verification role of the layout processing module will be discussed in Chapter 4. The actual task of converting Quartz layout information to explicit co-ordinates in LE-Pebble is handled by new stages in the distillation module. 3.7.3 Distillation of Size Expressions The distillation module actually converts Quartz descriptions into Pebble, eliminating higher- order parameters and other constructs that are not valid in Pebble. This module has been extended with code to compile layout expressions from Quartz into LE-Pebble. This is done in a recursive descent over expression trees, specifically eliminating height() and width() references. Three cases have to be dealt with: 1. The height()/width() function refers to a single block with domain and range signals linked into the local environment. In this case the block’s height or width expression is retrieved and compiled, before replacing the height()/width() function with appropriate substitutions for the correct applied domain/range signals. If the expression refers to signals internal to the block then these must be replaced with fresh identifiers and the code within the block that defines the values of these variables lifted into the current context. 2. The function refers to a parallel composition of blocks. This case is compiled by ap- plying the size interpretation of parallel compositions (function SIσ β) and extracting expressions for each block in the composition, combining them using either addition (height) or the max function (width). 3. The function refers to a series composition of blocks. In this case a similar operation must be employed as for parallel compositions however with a significant difference.
CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 59 If the generated size expression depends on internal signals hidden within the series composition then these must be explicitly instantiated. This is already the process that occurs when Quartz series compositions are compiled into Pebble and if the series composition exactly matches an instantiation carried out anyway then the same newly declared signals can be used. However, if the composition is not otherwise present in the block new variables must be declared and code that sets their values must be lifted into the local context. This implements the semantics of the definite description operator used in function SIσ β. 3.7.4 Recursive Size Expressions Many Quartz blocks have both recursive and iterative definitions. The two are usually equivalent, although the iterative versions compile more neatly into Pebble/VHDL. It is quite common to use the recursive definition of a common combinator for formal reasoning purposes and the iterative version in the generated hardware description. Some blocks, such as the binary tree combinator, can be more clearly defined recursively than iteratively. Size inference of recursively defined blocks can give recursive size expressions and while it is sometimes possible to manually specify iterative size expressions this is not always the case. The height and width of the recursively defined map combinator can be easily described using the same expressions as the iterative version, however the same can not be said for more complex combinators such as rows or grids where there are internal signals hidden by the recursion that can not be referenced or where blocks do not have a clearly defined size in terms of the simple sum and maxf functions (such as a tree). In any event, automation of this transformation is non-trivial so where size inference is used alone it is possible to be left with recursive size functions. For example, the recursively defined map combinator can be described by: map 0 R ⇔ id map n R ⇔ apln−1 −1 ; [R, map n−1 R] ; apln−1 After expanding the parallel composition, apl and id this gives size expressions for map n
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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APPENDIX D. CIRCUIT LAYOUT CASE STU
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