Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 57
processor also resolves overloading using an algorithm based around satisfiability matrix
predicates [64]. The standard output of the type processing module is a monomorphic,
annotated AST with multiple copies of polymorphic blocks instantiated for each utilised
type.
This output is suitable for the standard later stages of the compiler, however for placed
Quartz compilation we need to insert a new layout processing module between the type
processor and direction processor. This requires significant changes to the type processor to
split the instantiation stage in two, one part that resolves overloading and the other that
removes all polymorphism.
Since different overloaded instances of Quartz blocks can have different size expressions it
is necessary to resolve overloading prior to layout generation or layout verification. This is
achieved by the new “overloading resolution” stage within the type processor which replaces
references to overloaded blocks with references to specific instances, instantiating new copies
of blocks which use different overloaded instances on different occasions. This non-overloaded
but still polymorphic Quartz AST is then passed to the layout processing module.
After layout processing, the type processor completes the process of generating monomorphic
Quartz by eliminating all polymorphic types.
3.7.2 Layout Processing Module
The layout processing module, despite its name, does not take full responsibility for compiling
layout information in Quartz descriptions. It is responsible for initial processing of layout
information and preparation for later stages.
If the compiler is invoked on a design and is not requested to generate placed output the layout
processing module strips all size attributes and placement information from blocks. The
modified circuit design is then passed to the later compilation stages. If layout verification
or placed output mode is requested then the module checks that there are no unplaced
block instantiations within the circuit (unless they are the only instantiation within a block,
in which case they are automatically placed at (0, 0)) and then the size inference stage is
invoked.