Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 53
block surround (block A (‘a1, ‘a2) ∼ (‘a3, ‘a4),
(block B ‘l ∼ ‘a1, block C ‘t ∼ ‘a2),
(block D ‘a3 ∼ ‘b, block E ‘a4 ∼ ‘r))
(‘l l , ‘t t) ∼ (‘b b, ‘r r) {
‘a1 l2. ‘a2 t2. ‘a3 b2. ‘a4 r2.
l ; B ; l2 at (0, height(b2 ; D ; b)).
t ; C ; t2 at (width(l ; B ; l2), max(height(b2 ;D ;b) + height((l2,t2);A;(b2,r2)),
height(b2;D;b) + height(r2;E;r))).
(l2, t2) ; A ; (b2, r2) at (width(l ; B ; l2), height(b2 ; D ; b)).
b2 ; D ; b at (width(l ; B ; l2), 0).
r2 ; E ; r at (width(l ; B ; l2) + width((l2,t2);A;(b2,r2)), height(b2;D;b)).
}
Figure 3.14: A combinator describing the function and layout of the grid interface in Figure
3.13(b)
each block instantiation can be given explicit co-ordinates.
3. Since this arrangement is extremely common a new combinator can be created to
describe it.
4. A final alternative is to remove the layout interpretation from series and parallel com-
positions and require explicit co-ordinates within compositions. This is, in general,
more trouble than it is worth - however the option can be left open of not using explicit
co-ordinates and defaulting to the standard interpretation.
We would suggest option (3) is the most practical and flexible. The purpose of combining
explicit layout with combinators is to provide just this flexibility and a general combinator
implementing this structure is illustrated in Figure 3.14. This combinator appears complex
at first however it actually has a simple structure, with interface elements B, C, D and E
placed on the four sides of the square element A. Applied to the interface elements in the
grid example, this combinator is functionally identical:
Theorem 4
surround(grid m,n A, (map n B, map m B), (map m C, map n C)) =
[map n B, map m B] ; grid m,n A ; [map m C, map n C]