24.04.2013 Views

Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Verification of Parameterised FPGA Circuit Descriptions with Layout ...

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 51<br />

rippleadd is not a combinator and thus much simpler height and width expressions have been<br />

specified than would be inferred by the inference algorithm (though the result is the same).<br />

The zip and apr blocks are both pure wiring which require zero room so the row <strong>of</strong> full adders<br />

is the only block which actually contributes to the size <strong>of</strong> rippleadd - and since fadd has a<br />

constant height and width the size <strong>of</strong> the whole ripple adder can be described extremely<br />

clearly.<br />

Figure 3.12 shows the layout <strong>of</strong> the ripple adder circuit for n = 4.<br />

3.6 Different <strong>Layout</strong> Interpretations<br />

While functional descriptions <strong>of</strong> Quartz designs tend to have a useful obvious layout inter-<br />

pretation, it is <strong>of</strong>ten the case that designs have more than one possible layout interpretation.<br />

For example, the ripple adder illustrated as a row in Figure 3.12 could equally be described<br />

as a vertical array <strong>of</strong> full-adders. In this case we could use the col combinator rather than<br />

the row combinator however because Quartz combinators describe both function and layout<br />

it is sometimes desirable to use the same combinator <strong>with</strong> a different layout interpretation.<br />

For example, an m×n grid <strong>of</strong> A elements, surrounded by interface elements B on the domain<br />

and C on the range can be described in Quartz as:<br />

[map n B, map m B] ; grid m,n A ; [map m C, map n C]<br />

This is a common circuit structure, for example where blocks B and C could be input and<br />

output registers. However, the standard layout interpretation attached to Quartz constructs<br />

will produce the layout shown in Figure 3.13(a). This is not the worst possible layout that<br />

could be assigned to this circuit but it is far from compact <strong>with</strong> long wire lengths and a large<br />

area <strong>of</strong> unused logic resources.<br />

A better layout interpretation would be that shown in Figure 3.13(b). This layout can be<br />

enclosed in a much smaller bounding box and has shorter wires between the B and C elements<br />

and the grid. However, this layout is difficult to generate <strong>with</strong> the system as described so<br />

far.

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!