Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 50
block row (int n, block R (‘a, ‘b) ∼ (‘c, ‘a)) (‘a l , ‘b t[n]) ∼
(‘c b[n], ‘a r)
attributes {
height = maxf(k=0..n−1, height((is[k], t[k]) ;R ; (b[k], is [k+1]))).
width = sum(k=0..n−1, width ((is[k], t[k]) ;R ; (b[k], is [k+1]))).
} {
// Wires: l = left , t = top, b = bottom, r = right
int i. ‘a is [n+1].
is [0] = l.
for i = 0..n−1 {
(is [ i ], t[ i ]) ; R ; (b[i ], is [ i+1])
at (sum(k=0..i−1,width((is[k], t[k]) ; R ; (b[k], is [k+1]))), 0).
} .
r = is[n].
}
block fadd (wire cin, (wire a, wire b)) ∼ (wire ans, wire cout)
attributes { height = 1. width = 2. }{ }
block rippleadd (int n) (wire a[n], wire b[n]) ∼ (wire ans[n+1])
attributes {
height = 1.
width = 2 ∗ n.
} {
wire cin.
cin = false.
(cin, (a, b)) ; snd (zip 2) ; row (n, fadd) ; apr n ; ans at (0,0).
}
(0,0)
Figure 3.11: A simple placed ripple adder
fadd fadd fadd fadd
Figure 3.12: The ripple adder laid out on a grid for n = 4
(8,1)