Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 49
The general case requires a more general layout description, shown in Figure 3.10. Instead
of multiplication, the sum function is used to ensure that each block is placed at exactly the
right position and the sum and maxf functions are used to describe the bounding box for the
whole map n R block. Figure 3.9(c) demonstrates that this layout description can cope with
the irregular example.
It is worth noting that the manually specified height and width for this block are not the
same expressions that would be inferred by the inference algorithm in the previous section.
The inferred height expression would be:
maxf(j = 0..n − 1,width(i[j] ; R ; o[j]) + 0)
and the width expression would be:
maxf(j = 0..n − 1,height(i[j] ; R ; o[j]) +sum(k = 0..j − 1, height(i[k] ; R ; o[k]))
Both of these are more complex expressions than the manually specified expressions and this
is the main advantage of manually specifying size expressions rather than using the inference
algorithm. It is important to note that they are exactly equivalent (we will develop proofs
of this kind of relationship in Chapter 4).
3.5.3 A Placed Ripple Adder
A simple example of the kind of parameterised placed circuit that can be described with this
infrastructure is a ripple adder. The code in Figure 3.11 describes an n-bit ripple adder built
from a row of full-adder blocks (note that we have assumed that a full-adder block fadd is
available as a library/primitive element of size 2 × 1).
This description uses the row combinator, which has been annotated with placement infor-
mation, to generate a connected row of full adders. The rippleadd block uses the language
construct zip to re-arrange the tuple of vectors (a, b) into a vector of tuples for application
to the row of full adders and uses the wiring block apr (append-right) (in the Quartz prelude
library) to append the carry-out wire to the sum output.