Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 48
block map (int n, block R ‘a ∼ ‘b) (‘a i[n]) ∼ (‘b o[n])
attributes {
width = width(i[0] ;R ; o[0]) .
height = height(i[0] ; R ; o[0]) ∗ n.
} {
int j.
for j = 0..n−1 {
i [j] ; R ; o[j] at (0, height(i[0] ; R ; o[0]) ∗ j).
} .
}
(0, 3 * height R)
(0, 2 * height R)
(0, 1 * height R)
(0, 0)
Figure 3.8: The Quartz map n R combinator with naive layout information
R
R
R
R
(a) Naive layout
(width R, 4 * height R)
(0, 3 * height R)
(0, 2 * height R)
(0, 1 * height R)
(0, 0)
R
R
R
R
(width R, 4 * height R)
(b) Failure of naive layout
(0, height i[0];R;o[0] +
height i[1];R;o[1] +
height i[2];R;o[2])
(0, height i[0];R;o[0] +
height i[1];R;o[1])
(0, height i[0];R;o[0])
Figure 3.9: Different layouts for map n R
block map (int n, block R ‘a ∼ ‘b) (‘a i[n]) ∼ (‘b o[n])
attributes {
width = maxf(k=0..n−1, width (i[k] ;R ;o[k])).
height = sum(k=0..n−1, height (i[k] ;R ;o[k])).
} {
int j.
for j = 0..n−1 {
i [j] ; R ; o[j] at (0, sum(k=0..j−1,height(i[k] ;R ; o[k]))) .
} .
}
(0, 0)
R
R
R
R
(c) General layout
(max width R,
sum(j=0..3, height i[j];R;o[j])
Figure 3.10: The Quartz map n R combinator with general layout information