Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 43
SI :: SizeEnv → BlockEnv → Blkinst → (Exp × Exp)
SIσ β bid p1 . . . pn =
let (w, h) = σ(bid) in (w(p1 . . . pn), h(p1 . . . pn))
SIσ β [ b1 , . . . , bn ] =
let (w1, h1) = SIσ βb1 in
.
let (wn, hn) = SIσ βbn in
(λ(x1, . . .,xn)(y1, . . . , yn). max(w1(x1, y1), . . . , wn(xn, yn)),
λ(x1, . . . , xn)(y1, . . .,yn). h1(x1, y1) + · · · + hn(xn, yn))
SIσ β b1 ; b2 =
let (w1, h1) = SIσ βb1 in
let (w2, h2) = SIσ βb2 in
(λxy. let s = (ιs. B ′ β b1(x, s) ∧ B ′ β b2(s, y)) in w1(x, s) + w2(s, y),
λxy. let s = (ιs. B ′ β b1(x, s) ∧ B ′ β b2(s, y)) in max(h1(x, s), h2(s, y)))
Figure 3.4: Calculating a size function for a block instantiation
S
R
T
(a) Parallel composition
R
S
T
(b) Series composition
Figure 3.5: Sizes generated for block compositions