Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 42
E :: SizeEnv → BlockEnv → V arEnv → Exp → Exp
Eσ β µ height(x ; bs ; y) =
let (w,h) = SIσ βbs in Eσ β µh(x, y)
Eσ β µ width(x ; bs ; y) =
let (w,h) = SIσ βbs in Eσ β µw(x, y)
Eσ β µ max(e1, e2, . . . , en) =
let e ′ 1 = Eσ β µe1 in
let e ′ 2 = Eσ β µe2 in
.
let e ′ n = Eσ β µen in
max (e ′ 1 , e′ 2 , . . ., e′ n)
Eσ β µ sum(i = e1..e2, f) =
let e ′ 2 = Eσ β µe2 in
if e ′ 2 < Eσ β µe1 then 0
else Eσ β µ{i ↦→ e ′ 2 }f+sum(i = e1..(e ′ 2
Eσ β µ maxf(i = e1..e2, f) =
− 1), f)
let e ′ 1 = Eσ β µe1 in let e ′ 2 = Eσ β µe2 in
if e ′ 2 < e′ 1 then 0
else if e ′ 2 = e′ 1 then {i ↦→ e′ 2 }f
else Eσ β µmax({i ↦→ e ′ 2 }f, maxf(i = e1..(e ′ 2 − 1), f))
Figure 3.3: Semantics of size expressions
Proof Theorem 2 is proved by expanding the definitions of min and max and re-arranging.
Theorem 3 is proved by analysing the cases where e1 > e2 and e1 ≤ e2 separately. In the
first case, both functions return zero and thus the proposition holds, in the latter case proof
is by induction on e2 (with a base case of e1 = e2) and then re-arrangement using Theorem
2. Mechanised proofs are given as theorems min max corres and minf maxf corres in
Appendix B.11.
3.4.2 Size of Block Instantiations
The function SIσ β returns the size functions for a particular block instantiation. It is
parameterised by two environments, σ maps block identifiers to a pair of (width, height)
functions, β maps block identifiers to their definition. The function definition can be seen in
Figure 3.4. The semantic function for blocks, Bβ, generates a logical predicate corresponding
to the definition of a block identifier, SIσ β uses the function B ′ β which carries out the same
operation for block instantiation statements. These functions are defined in Figure 4.8 on
page 81 however their precise definition is mainly relevant to layout verification in Chapter 4
rather than compilation.