Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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Table of Contents 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Background and Related Work 6 2.1 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 Generating FPGA Circuits . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Layout Information in Hardware Descriptions . . . . . . . . . . . . . . 8 2.1.3 FPGA Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Describing Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 High Level Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Lower Level Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Quartz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Type System and Overloading . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 Formal Reasoning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 Automated Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.1 Model Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.2 Theorem Proving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.3 Comparison with Model Checking . . . . . . . . . . . . . . . . . . . . 24 2.4.4 Logic and Proof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.5 Theorem Proving Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.6 Embeddings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 iii
TABLE OF CONTENTS iv 2.5 Isabelle: A Generic Theorem Prover . . . . . . . . . . . . . . . . . . . . . . . 28 2.5.1 Meta-logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5.2 Theories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.5.3 Unification, Resolution and Proof . . . . . . . . . . . . . . . . . . . . . 31 2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 Generating Parameterised Libraries with Layout 34 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 Placement Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4 Block Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.1 Size Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.2 Size of Block Instantiations . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.3 Size Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5 Parameterised Quartz with Placement . . . . . . . . . . . . . . . . . . . . . . 46 3.5.1 Laid-out Combinators . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.2 Naive vs General Placement . . . . . . . . . . . . . . . . . . . . . . . . 47 3.5.3 A Placed Ripple Adder . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6 Different Layout Interpretations . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.6.1 Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.2 Combinators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.7 Compiling Placed Quartz Designs . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.7.1 Changes to the Type Processing Module . . . . . . . . . . . . . . . . . 56 3.7.2 Layout Processing Module . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7.3 Distillation of Size Expressions . . . . . . . . . . . . . . . . . . . . . . 58 3.7.4 Recursive Size Expressions . . . . . . . . . . . . . . . . . . . . . . . . 59 3.7.5 Expression Simplification . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.8 Compiling LE-Pebble into VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.9 Summary and Comparison with Related Work . . . . . . . . . . . . . . . . . 63 4 Verifying Circuit Layouts 65 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Page 1 and 2: Imperial College of Science, Techno
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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