Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 38
〈stmt〉 ::= assert (〈expr〉) "〈string〉" .
| 〈expr〉 = 〈expr〉 .
| 〈arg〉 ; 〈blkref 〉 (; 〈blkref 〉 )* ; 〈arg〉 .
| for 〈id〉 = 〈expr〉..〈expr〉 { 〈stmt〉* } .
| if (〈expr〉) { 〈stmt〉* } ( else { 〈stmt〉* } )? .
〈blkref 〉 ::= 〈id〉 〈arg〉* | [ ] | [ 〈blkref 〉 (, 〈blkref 〉)* ]
〈arg〉 ::= 〈id〉 〈vecindex 〉 | 〈expr〉
| ( ) | ( 〈arg〉 (, 〈arg〉)* )
Figure 3.1: Grammar of Quartz statements
itself, which describes the size of the statements within the block.
Assertion statements are compile-time directives that check for the validity of particular pre-
conditions and thus have no effect on the resulting layout. The assignment operation has
three (overloaded) uses:
1. Assigning values to variables which may control elaboration.
2. Assigning static values to wires.
3. Connecting wires together.
(1) clearly does not have any direct effect on layout (save that it may affect the way later
statements are processed). In our model that concentrates on layout rather than routing we
will assume that (2) and (3) also have no effect on layout. This is a reasonable assumption
since FPGA routing resources are independent from computational ones and it is not generally
necessary to allocate computational logic resources to either of these functions 1 .
Conditional statements allow different hardware to be generated depending on the evaluation
of a boolean expression. This is significant because the two possible branches of the condi-
tional can have different sizes and thus any reference to the size of the overall conditional
must take this into account. The easiest way to do this is to allow placement expressions to
contain conditionals of their own, a simple and remarkably powerful approach.
Loops allow the instantiation of multiple hardware blocks. An important realisation for the
1 Issues with insufficient routing resources are unusual in most cases when using the standard placer and
router. However, if a lot of logic is packed with LOC/RLOC constraints regardless of the available routing
resources this could increase the risk of routing congestion making it possible to describe circuits that can
not be routed.