Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 3. GENERATING PARAMETERISED LIBRARIES WITH LAYOUT 35
a badly placed design will feature unnecessary long wire lengths with accompanying delays
and impact on maximum clock frequency.
While modern place and route systems based on simulated annealing can achieve excellent
results for the highest performance it is still common to intervene manually in the placement
of designs and much of the value of Intellectual Property Cores, such as those produced by the
Xilinx Core Generator tool, is that they are carefully laid out to provide good performance.
Manual placement is of particular value when a human designer can recognise and exploit an
underlying regularity in a high level description.
Ensuring optimal resource use and layout is particularly important for parameterised hard-
ware libraries since any inefficiency will affect all designs that use them. Controlling place-
ment is also desirable for reconfigurable circuits to support partial reconfiguration, since
identical components at identical locations common to two different configurations do not
need to be reconfigured when switching between them.
The Xilinx “RLOC” placement macro allows primitive hardware components to be placed
relative to each other in a structural design description. RLOCs provide a relatively low-level
interface to influence the place and route system and allow the production of parameterised,
fully or partially laid out designs in a conventional hardware description language like VHDL
or Verilog. However, supplying explicit coordinate information for every component in a
large circuit is tedious and error-prone.
Relative placement, laying out components beside or below one another, has been proposed
for producing designs. Systems that support this technique include Ruby [26], Lava [7] and
Pebble [49, 50]. Neither the Ruby-based or Lava-based systems that have been developed
maintain full parameterisation while processing layout, something that makes them unsuit-
able if the desired goal is to produce parameterised library descriptions. The Pebble system
does maintain parameterisation while converting relative positions into explicit coordinates
however the generated layouts are not necessarily optimal and designers are restricted to
using relative positioning only, without any explicit coordinates.
In this chapter we develop a system that allows the combination of relative and explicit
placement information in a single framework and the compilation of these descriptions into