Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Chapter 3
Generating Parameterised
Libraries with Layout
In this chapter we describe how the Quartz framework can be extended to allow the generation
of parameterised hardware libraries with layout information. Section 3.1 introduces our
motivation for supporting hand placement of designs and discusses the benefits of relative
placement. Section 3.2 introduces the basic concepts behind our placement infrastructure
and Section 3.3 discusses what is required to provide language support for hand placement in
Quartz. Section 3.4 demonstrates how block sizes can be described by extending the class of
Quartz expressions and Section 3.5 demonstrates how the Quartz layout system can describe
parameterised combinators and full designs. Section 3.6 shows how blocks can be given
multiple layout interpretations. Section 3.7 describes the compilation of placed Quartz into
an extended version of Pebble 5, while Section 3.8 describes how this can then be compiled
into parameterised VHDL. Section 3.9 summarises this chapter and discusses related work.
3.1 Introduction
Placement and routing are critical steps in the compilation of a high-level hardware de-
scription onto the reconfigurable fabric of a FGPA. The effectiveness of the placement and
routing algorithms has a significant impact on the performance of the resulting circuit since
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