Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 310 t805)vector)vector)=>((’t686)vector*(’t805)vector)vector=>int)block) ;; col $ (z, swap ;; rsh ;; fst $ (zip $ 2) ;; grid $ (x, y, cube_cell $ (x, R)) ;; snd $ (converse $ (zip $ 2)) ;; rsh ;; fst $ swap ;; lsh) ;; snd $ (converse $ ((zip $ 2)::((((’t805)vector)vector*((’t686)vector)vector)=>((’t805)vector *(’t686)vector)vector=>bool,(((’t805)vector)vector*((’t686)vector)vector) =>((’t805)vector*(’t686)vector)vector=>int)block)) ;;; (z_r, (y_r, x_r)))" width_def: "width == % (x, y, z, R) (x_d, y_d, z_d) (z_r, y_r, x_r). Width (((x_d , y_d), z_d) ;;; fst $ ((zip $ 2)::((((’t686)vector)vector*((’t805)vector) vector)=>((’t686)vector*(’t805)vector)vector=>bool,(((’t686)vector)vector*((’ t805)vector)vector)=>((’t686)vector*(’t805)vector)vector=>int)block) ;; col $ (z, swap ;; rsh ;; fst $ (zip $ 2) ;; grid $ (x, y, cube_cell $ (x, R)) ;; snd $ (converse $ (zip $ 2)) ;; rsh ;; fst $ swap ;; lsh) ;; snd $ (converse $ ((zip $ 2)::((((’t805)vector)vector*((’t686)vector)vector)=>((’t805)vector *(’t686)vector)vector=>bool,(((’t805)vector)vector*((’t686)vector)vector) =>((’t805)vector*(’t686)vector)vector=>int)block)) ;;; (z_r, (y_r, x_r)))" cube_def: "cube == (| Def = struct, Height = height, Width = width |)" declare width_def [simp] declare height_def [simp] declare struct_def [simp] section {* Validity <strong>of</strong> width and height functions *} theorem height_ge0_int : "!! (x::int) (y::int) (z::int) (R::(((’t686*’t805*’t772)=>(’ t772*’t805*’t686)=>bool,(’t686*’t805*’t772)=>(’t772*’t805*’t686)=>int)block)) ( x_d::((’t686)vector)vector) (y_d::((’t805)vector)vector) (z_d::((’t772)vector) vector) (z_r::((’t772)vector)vector) (y_r::((’t805)vector)vector) (x_r::((’t686) vector)vector). [| ALL (qs1103::(’t686*’t805*’t772)) (qs1104::(’t772*’t805*’t686 )). 0 bool,(’t686*’t805*’t772)=>(’t772*’t805*’t686)=>int)block)) ( x_d::((’t686)vector)vector) (y_d::((’t805)vector)vector) (z_d::((’t772)vector) vector) (z_r::((’t772)vector)vector) (y_r::((’t805)vector)vector) (x_r::((’t686) vector)vector). [| ALL (qs1103::(’t686*’t805*’t772)) (qs1104::(’t772*’t805*’t686 )). 0 bool,(’t686*’t805*’t772)=>(’t772*’t805*’t686)=>int)block)) (x_d
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 311 ::((’t686)vector)vector) (y_d::((’t805)vector)vector) (z_d::((’t772)vector) vector) (z_r::((’t772)vector)vector) (y_r::((’t805)vector)vector) (x_r::((’t686) vector)vector). [| ALL (qs1103::(’t686*’t805*’t772)) (qs1104::(’t772*’t805*’t686 )). 0 bool,(’t686*’t805*’t772)=>(’t772*’t805*’t686)=>int)block)) (x_d ::((’t686)vector)vector) (y_d::((’t805)vector)vector) (z_d::((’t772)vector) vector) (z_r::((’t772)vector)vector) (y_r::((’t805)vector)vector) (x_r::((’t686) vector)vector). [| ALL (qs1103::(’t686*’t805*’t772)) (qs1104::(’t772*’t805*’t686 )). 0 bool,(’t686*’t805*’t772)=>(’t772*’t805*’t686)=>int)block)) (x_d::((’t686) vector)vector) (y_d::((’t805)vector)vector) (z_d::((’t772)vector)vector) (z_r ::((’t772)vector)vector) (y_r::((’t805)vector)vector) (x_r::((’t686)vector) vector). [| Def (((x_d, y_d), z_d) ;;; fst $ (zip $ 2) ;; col $ (z, swap ;; rsh ;; fst $ (zip $ 2) ;; grid $ (x, y, cube_cell $ (x, R)) ;; snd $ (converse $ ( zip $ 2)) ;; rsh ;; fst $ (swap) ;; lsh) ;; snd $ (converse $ (zip $ 2)) ;;; ( z_r, (y_r, x_r))) ; ALL (qs1103::(’t686*’t805*’t772)) (qs1104::(’t772*’t805*’ t686)). 0 ((’t686) vector*(’t805)vector)vector=>int)block) ;; col $ (z, swap ;; rsh ;; fst $ (zip $ 2) ;; grid $ (x, y, cube_cell $ (x, R)) ;; snd $ (converse $ (zip $ 2)) ;; rsh ;; fst $ swap ;; lsh) ;; snd $ (converse $ ((zip $ 2)::((((’t805)vector)vector *((’t686)vector)vector)=>((’t805)vector*(’t686)vector)vector=>bool,(((’t805) vector)vector*((’t686)vector)vector)=>((’t805)vector*(’t686)vector)vector=>int) block)) ;;; (z_r, (y_r, x_r))))) ((’t686)vector*(’t805)vector )vector=>bool,(((’t686)vector)vector*((’t805)vector)vector)=>((’t686)vector*(’ t805)vector)vector=>int)block) ;; col $ (z, swap ;; rsh ;; fst $ (zip $ 2) ;; grid $ (x, y, cube_cell $ (x, R)) ;; snd $ (converse $ (zip $ 2)) ;; rsh ;; fst $ swap ;; lsh) ;; snd $ (converse $ ((zip $ 2)::((((’t805)vector)vector*((’t686) vector)vector)=>((’t805)vector*(’t686)vector)vector=>bool,(((’t805)vector)vector *((’t686)vector)vector)=>((’t805)vector*(’t686)vector)vector=>int)block)) ;;; ( z_r, (y_r, x_r))))) &
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 109 opera
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 115 const
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CHAPTER 5. SPECIALISATION 117 block
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 121 Buffe
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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