Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 306
}
cin = false.
(a, b) ; zip 2 ; converse (pi1) ; col (n, fadd clk) ; (cin, ans) at (0,0).
/∗ Repeating cell for cubical matrix multiplier ∗/
block matmultcell (int n) (wire clk) (wire x in[n], wire y in[n], wire z in[n]) ∼
(wire z out[n], wire y out[n], wire x out[n]) {
x out = x in.
y out = y in.
((x in, y in), z in) ; fst (mult n) ; add n clk; z out at (0,0).
}
/∗∗ Transpose a matrix ∗/
block word transpose (int bits) (int n, int m) (‘a v1[n][m][bits ]) ∼ (‘a v2[m][n][ bits ]) {
int i , j.
for i = 0..n−1 {
for j = 0..m−1 {
v2[j ][ i ] = v1[i ][ j].
} . } .
}
/∗∗ Matrix multiplier ∗/
block matmult (wire clk) (int bits) (int x, int y, int z)
(wire mat1[y][z ][ bits ], wire mat2[z][x][ bits ]) ∼ (wire mat3[y][x][ bits ]) {
wire emptymat[y][x][bits].
wire mat trans[z][y][ bits ].
int i , j, k.
for i = 0..y−1 { for j = 0..x−1 { for k = 0..bits−1 { emptymat[i][j][ k] = false. } . } . } .
mat1 ; word transpose bits (y, z) ; mat trans at (0,0).
(mat trans, mat2, emptymat) ;
cube (x, y, z, matmultcell bits clk) ;
converse (tplapl 2) ;
pi1 ;
mat3 at (0,0).
}
D.3.2 Theory cube cell
theory cube_cell = apr + lsh + swap + fst + rsh + apl + converse + snd:
section {* Temporary definitions to support tplapl in Isabelle *}
constdefs
tplapr2_struct :: "((’a*’b)*’c)=>(’a*’b*’c)=>bool"
"tplapr2_struct == (% ((a, b), c) (d, e, f). a = d & b = e & f = c)"
tplapr2 :: "(((’a*’b)*’c)=>(’a*’b*’c)=>bool,((’a*’b)*’c)=>(’a*’b*’c)=>int)block"
"tplapr2 == (| Def = tplapr2_struct, Height = % a b. (0::int), Width = % a b.
(0::int) |)"
tplapl2_struct :: "(’a*(’b*’c))=>(’a*’b*’c)=>bool"
"tplapl2_struct == (% (a, (b, c)) (d, e, f). a = d & b = e & c = f)"
tplapl2 :: "((’a*(’b*’c))=>(’a*’b*’c)=>bool,(’a*(’b*’c))=>(’a*’b*’c)=>int)block"
"tplapl2 == (| Def = tplapl2_struct, Height = % a b. (0::int), Width = % a b.
(0::int) |)"
section {* Function definitions *}
consts