Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 304
height_def: "height == % clk bits n (a, b) c. let m = (2 pwr n) in Height ((a, b)
;;; snd $ (rev $ (m div 2)) ;; converse $ (half $ (m div 2)) ;; butterfly $
(n, sort2 $ clk $ bits) ;;; c)"
width_def: "width == % clk bits n (a, b) c. let m = (2 pwr n) in Width ((a, b)
;;; snd $ (rev $ (m div 2)) ;; converse $ (half $ (m div 2)) ;; butterfly $ (
n, sort2 $ clk $ bits) ;;; c)"
merger_def: "merger == (| Def = struct, Height = height, Width = width|)"
declare width_def [simp]
declare height_def [simp]
declare struct_def [simp]
section {* Validity of width and height functions *}
theorem height_ge0_int : "!! (clk::wire) (bits::int) (n::int) (a::((wire)vector)
vector) (b::((wire)vector)vector) (c::((wire)vector)vector). 0