Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 296 } (a,b) ; snd (rev (m/2)) ; converse (half (m/2)) ; butterfly (n, sort2) ; c at (0,0). D.2.2 Theory comparator theory comparator = pi1 + comp_elem + rdr + fst: section {* Function definitions *} consts struct:: "int=>((wire)vector*(wire)vector)=>wire=>bool" height:: "int=>((wire)vector*(wire)vector)=>wire=>int" width:: "int=>((wire)vector*(wire)vector)=>wire=>int" comparator:: "(int=>((wire)vector*(wire)vector)=>wire=>bool, int=>((wire)vector*( wire)vector)=>wire=>int)block" defs struct_def: "struct == % bits (a, b) a_gr_b. EX (zero::wire) (one::wire). (zero = (bool2wire False)) & (one = (bool2wire True)) & Def (((a, b), (zero, one)) ;;; fst $ (zip $ 2) ;; rdr $ (bits, comp_elem) ;; pi1 ;;; a_gr_b)" height_def: "height == % bits (a, b) a_gr_b. let (zero, one) = (THE (zero::wire, one::wire). (zero = (bool2wire False)) & (one = (bool2wire True)) & Def (((a, b), (zero, one)) ;;; fst $ (zip $ 2) ;; rdr $ (bits, comp_elem) ;; pi1 ;;; a_gr_b)) in max (Height (((a, b), (zero, one)) ;;; fst $ (zip $ 2) ;; rdr $ ( bits, comp_elem) ;; pi1 ;;; a_gr_b)) 0" width_def: "width == % bits (a, b) a_gr_b. let (zero, one) = (THE (zero::wire, one::wire). (zero = (bool2wire False)) & (one = (bool2wire True)) & Def (((a, b), (zero, one)) ;;; fst $ (zip $ 2) ;; rdr $ (bits, comp_elem) ;; pi1 ;;; a_gr_b)) in max (Width (((a, b), (zero, one)) ;;; fst $ (zip $ 2) ;; rdr $ ( bits, comp_elem) ;; pi1 ;;; a_gr_b)) 0" comparator_def: "comparator == (| Def = struct, Height = height, Width = width |) " declare width_def [simp] declare height_def [simp] declare struct_def [simp] section {* Validity of width and height functions *} theorem height_ge0_int : "!! (bits::int) (a::(wire)vector) (b::(wire)vector) (a_gr_b ::wire). 0
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 297 apply (simp (no_asm_simp) del: height_def width_def add: Let_def max_def fst_def zip_def rdr_def comp_elem_def pi1_def comparator_def, (rule height_ge0_int, (simp+)?)?) done theorem width_ge0: "!! (bits::int) (a::(wire)vector) (b::(wire)vector) (a_gr_b::wire) . 0 ((0::int) bool" height:: "wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=> int" width:: "wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=>int " sort2:: "(wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=> bool, wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=> int)block" defs struct_def: "struct == % clk bits (a, b) (min_val, max_val). EX (a_gr_b::wire). Def ((a, b) ;;; comparator $ bits ;;; a_gr_b) & Def ((a, b) ;;; zip $ 2 ;; map $ (bits, register $ clk $ (mux_lut $ a_gr_b)) ;;; min_val) & Def ((b, a) ;;; zip $ 2 ;; map $ (bits, register $ clk $ (mux_lut $ a_gr_b)) ;;; max_val) " height_def: "height == % clk bits (a, b) (min_val, max_val). let a_gr_b = (THE ( a_gr_b::wire). Def ((a, b) ;;; comparator $ bits ;;; a_gr_b) & Def ((a, b) ;;; zip $ 2 ;; map $ (bits, register $ clk $ (mux_lut $ a_gr_b)) ;;; min_val) & Def ((b, a) ;;; zip $ 2 ;; map $ (bits, register $ clk $ (mux_lut $ a_gr_b
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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 297<br />
apply (simp (no_asm_simp) del: height_def width_def add: Let_def max_def fst_def<br />
zip_def rdr_def comp_elem_def pi1_def comparator_def,<br />
(rule height_ge0_int, (simp+)?)?)<br />
done<br />
theorem width_ge0: "!! (bits::int) (a::(wire)vector) (b::(wire)vector) (a_gr_b::wire)<br />
. 0 <br />
((0::int) <br />
bool"<br />
height:: "wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=><br />
int"<br />
width:: "wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=>int<br />
"<br />
sort2:: "(wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=><br />
bool, wire=>int=>((wire)vector*(wire)vector)=>((wire)vector*(wire)vector)=><br />
int)block"<br />
defs<br />
struct_def: "struct == % clk bits (a, b) (min_val, max_val). EX (a_gr_b::wire).<br />
Def ((a, b) ;;; comparator $ bits ;;; a_gr_b) & Def ((a, b) ;;; zip $ 2 ;;<br />
map $ (bits, register $ clk $ (mux_lut $ a_gr_b)) ;;; min_val) & Def ((b, a)<br />
;;; zip $ 2 ;; map $ (bits, register $ clk $ (mux_lut $ a_gr_b)) ;;; max_val)<br />
"<br />
height_def: "height == % clk bits (a, b) (min_val, max_val). let a_gr_b = (THE (<br />
a_gr_b::wire). Def ((a, b) ;;; comparator $ bits ;;; a_gr_b) & Def ((a, b)<br />
;;; zip $ 2 ;; map $ (bits, register $ clk $ (mux_lut $ a_gr_b)) ;;; min_val)<br />
& Def ((b, a) ;;; zip $ 2 ;; map $ (bits, register $ clk $ (mux_lut $ a_gr_b
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