Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 295
}
wire o2.
i ; R ; o2 at (0,0).
o2 ; fd clk ; o at (0,0).
block and3 (wire a, wire b, wire c) ∼ (wire d)
attributes { height = 1. width = 1. }{ }
block mux lut (wire s) (wire d0, wire d1) ∼ (wire o)
attributes { height = 1. width = 1. }{ }
block gr lut ((wire a, wire b), (wire is gr, wire is eq)) ∼ (wire is gr2)
attributes { height = 1. width = 1. }{ }
block eq lut ((wire a, wire b), wire is eq) ∼ (wire is eq2)
attributes { height = 1. width = 1. }{ }
block comp elem ((wire a, wire b), (wire is gr, wire is eq)) ∼ (wire is gr2, wire is eq2) {
((a, b), (is gr, is eq)) ; gr lut ; is gr2 at (0, 0).
((a, b), is eq) ; eq lut ; is eq2 at (1, 0).
}
block comparator (int bits) (wire a[bits ], wire b[bits ]) ∼ (wire a gr b) {
wire zero, one.
zero = false. one = true.
((a, b), (zero, one)) ; fst (zip 2) ; rdr (bits, comp elem) ;pi1 ; a gr b at (0,0).
}
/∗ Two input sorting circuit with output register ∗/
block sort2 (wire clk) (int bits) (wire a[bits ], wire b[bits ]) ∼
(wire min val[bits], wire max val[bits]) {
wire a gr b.
(a, b) ; comparator (bits) ; a gr b at (0,0).
(a, b) ; zip 2 ; map (bits, register clk (mux lut a gr b)) ;min val at (width((a, b) ;
comparator (bits) ; a gr b), 0).
(b, a) ; zip 2 ; map (bits, register clk (mux lut a gr b)) ;max val at (width((a, b) ;
comparator (bits) ;a gr b) + width((a, b) ;zip 2 ; map (bits, mux lut a gr b) ;
min val), 0).
}
block vecpair (‘a i [2]) ∼ (‘a o1, ‘a o2) → (o1, o2) = (i [0], i [1]) .
/∗ Combinator describing an arbitrary butterfly network ∗/
block butterfly (int n, block R (‘a, ‘a) ∼ (‘a, ‘a)) (‘a l[m]) ∼ (‘a r[m]) {
const m = 2 ∗∗ n.
l ; rcomp (n,
riffle (m/2) ;
pair (m/2) ;
map (m/2, vecpair ; R ; converse (vecpair)) ;
converse (pair (m/2))
)
; r.
}
/∗ Pipelined bitonic merger ∗/
block merger (int n) (wire a[m/2], wire b[m/2]) ∼ (wire c[m]) {
const m = 2∗∗n.