Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 294 done Let_def max_def) section {* Additional simplification rules for different representations *} theorem height_ge0: "!! (n::int) (bits::int) (clk::wire) (newval::(wire)vector) ( median::(wire)vector). 0
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 295 } wire o2. i ; R ; o2 at (0,0). o2 ; fd clk ; o at (0,0). block and3 (wire a, wire b, wire c) ∼ (wire d) attributes { height = 1. width = 1. }{ } block mux lut (wire s) (wire d0, wire d1) ∼ (wire o) attributes { height = 1. width = 1. }{ } block gr lut ((wire a, wire b), (wire is gr, wire is eq)) ∼ (wire is gr2) attributes { height = 1. width = 1. }{ } block eq lut ((wire a, wire b), wire is eq) ∼ (wire is eq2) attributes { height = 1. width = 1. }{ } block comp elem ((wire a, wire b), (wire is gr, wire is eq)) ∼ (wire is gr2, wire is eq2) { ((a, b), (is gr, is eq)) ; gr lut ; is gr2 at (0, 0). ((a, b), is eq) ; eq lut ; is eq2 at (1, 0). } block comparator (int bits) (wire a[bits ], wire b[bits ]) ∼ (wire a gr b) { wire zero, one. zero = false. one = true. ((a, b), (zero, one)) ; fst (zip 2) ; rdr (bits, comp elem) ;pi1 ; a gr b at (0,0). } /∗ Two input sorting circuit <strong>with</strong> output register ∗/ block sort2 (wire clk) (int bits) (wire a[bits ], wire b[bits ]) ∼ (wire min val[bits], wire max val[bits]) { wire a gr b. (a, b) ; comparator (bits) ; a gr b at (0,0). (a, b) ; zip 2 ; map (bits, register clk (mux lut a gr b)) ;min val at (width((a, b) ; comparator (bits) ; a gr b), 0). (b, a) ; zip 2 ; map (bits, register clk (mux lut a gr b)) ;max val at (width((a, b) ; comparator (bits) ;a gr b) + width((a, b) ;zip 2 ; map (bits, mux lut a gr b) ; min val), 0). } block vecpair (‘a i [2]) ∼ (‘a o1, ‘a o2) → (o1, o2) = (i [0], i [1]) . /∗ Combinator describing an arbitrary butterfly network ∗/ block butterfly (int n, block R (‘a, ‘a) ∼ (‘a, ‘a)) (‘a l[m]) ∼ (‘a r[m]) { const m = 2 ∗∗ n. l ; rcomp (n, riffle (m/2) ; pair (m/2) ; map (m/2, vecpair ; R ; converse (vecpair)) ; converse (pair (m/2)) ) ; r. } /∗ Pipelined bitonic merger ∗/ block merger (int n) (wire a[m/2], wire b[m/2]) ∼ (wire c[m]) { const m = 2∗∗n.
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 109 opera
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 115 const
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CHAPTER 5. SPECIALISATION 117 block
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 121 Buffe
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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