Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 291
(rule allI)+,
(case_tac "0 ((wire)vector*((wire)vector)vector)=>(((wire)vector)
vector*(wire)vector)=>bool"
height:: "(int*int)=>wire=>((wire)vector*((wire)vector)vector)=>(((wire)vector)
vector*(wire)vector)=>int"
width:: "(int*int)=>wire=>((wire)vector*((wire)vector)vector)=>(((wire)vector)
vector*(wire)vector)=>int"
filter_core:: "((int*int)=>wire=>((wire)vector*((wire)vector)vector)=>(((wire)
vector)vector*(wire)vector)=>bool, (int*int)=>wire=>((wire)vector*((wire)
vector)vector)=>(((wire)vector)vector*(wire)vector)=>int)block"
defs
struct_def: "struct == % (n, bits) clk (newval, s) (s2, median). Def ((newval, s)
;;; fst $ (fork ;; fst $ (rcomp $ (n, map $ (bits, fd $ clk)))) ;; below $ (
nextstate $ clk $ bits $ n, insert_median $ bits $ n) ;; snd $ (pi2) ;;; (s2,
median))"
height_def: "height == % (n, bits) clk (newval, s) (s2, median). Height ((newval,
s) ;;; fst $ (fork ;; fst $ (rcomp $ (n, map $ (bits, fd $ clk)))) ;; below
$ (nextstate $ clk $ bits $ n, insert_median $ bits $ n) ;; snd $ (pi2) ;;; (
s2, median))"
width_def: "width == % (n, bits) clk (newval, s) (s2, median). Width ((newval, s)
;;; fst $ (fork ;; fst $ (rcomp $ (n, map $ (bits, fd $ clk)))) ;; below $ (
nextstate $ clk $ bits $ n, insert_median $ bits $ n) ;; snd $ (pi2) ;;; (s2,
median))"
filter_core_def: "filter_core == (| Def = struct, Height = height, Width = width
|)"
declare width_def [simp]
declare height_def [simp]
declare struct_def [simp]
section {* Validity of width and height functions *}
theorem height_ge0_int : "!! (n::int) (bits::int) (clk::wire) (newval::(wire)vector)
(s::((wire)vector)vector) (s2::((wire)vector)vector) (median::(wire)vector). 0