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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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Acknowledgements<br />

Firstly, I’d like to thank my supervisor, Wayne Luk, for invaluable discussions and support<br />

throughout this project and the work that has preceded it.<br />

I’d also like to thank all the past and present members <strong>of</strong> the Custom Computing research<br />

group for general help and advice. Particular thanks are due to Tobias Becker, Jacob Bower,<br />

Arran Derbyshire, Rob Dimond and Henry Styles for pointing me in interesting directions,<br />

reading drafts, stating the obvious when I had missed it or simply sharing their experience<br />

<strong>of</strong> where it’s best to aim kicks at expensive bits <strong>of</strong> <strong>FPGA</strong> hardware in order to get them to<br />

do what you want them to.<br />

I owe a debt <strong>of</strong> gratitude to those who have developed the tools I have used in this project,<br />

most especially the people at University <strong>of</strong> Cambridge, TU Munich and elsewhere who are<br />

responsible for Isabelle. Thanks are definitely due to the members <strong>of</strong> the isabelle-users<br />

mailing list, particularly Larry Paulson and Tobias Nipkow, for answering my Isabelle-related<br />

questions.<br />

Finally, I’d like to thank the friends and family who have put up <strong>with</strong> me all these years and<br />

especially Nia who has had to listen to me talk endlessly about hardware verification and<br />

synthesis and yet has managed, most <strong>of</strong> the time, to pretend that it is interesting.<br />

ii

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