Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 282 )) + (Height ((a, s) ;;; eq $ bits ;;; a_eq_s))) (wire)vector=>bool" height:: "int=>int=>((wire)vector*((wire)vector)vector)=>(wire)vector=>int" width:: "int=>int=>((wire)vector*((wire)vector)vector)=>(wire)vector=>int" locater:: "(int=>int=>((wire)vector*((wire)vector)vector)=>(wire)vector=>bool, int=>int=>((wire)vector*((wire)vector)vector)=>(wire)vector=>int)block" defs struct_def: "struct == % bits n (a, s) d. EX (found::wire). (found = bool2wire False) & Def (((found, a), s) ;;; row $ (n + 1, lct_cell $ bits) ;; pi1 ;;; d )" height_def: "height == % bits n (a, s) d. let found = (THE (found::wire). (found = bool2wire False) & Def (((found, a), s) ;;; row $ (n + 1, lct_cell $ bits) ;; pi1 ;;; d)) in max (Height (((found, a), s) ;;; row $ (n + 1, lct_cell $ bits) ;; pi1 ;;; d)) 0" width_def: "width == % bits n (a, s) d. let found = (THE (found::wire). (found = bool2wire False) & Def (((found, a), s) ;;; row $ (n + 1, lct_cell $ bits) ;; pi1 ;;; d)) in max (Width (((found, a), s) ;;; row $ (n + 1, lct_cell $ bits ) ;; pi1 ;;; d)) 0" locater_def: "locater == (| Def = struct, Height = height, Width = width |)" declare width_def [simp] declare height_def [simp] declare struct_def [simp] section {* Validity of width and height functions *} theorem height_ge0_int : "!! (bits::int) (n::int) (a::(wire)vector) (s::((wire)vector )vector) (d::(wire)vector). 0
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 283 done theorem width_ge0_int : "!! (bits::int) (n::int) (a::(wire)vector) (s::((wire)vector) vector) (d::(wire)vector). 0 ((wire)vector*((wire)vector*wire))=>((wire)vector*(wire) vector)=>int" width:: "wire=>int=>((wire)vector*((wire)vector*wire))=>((wire)vector*(wire) vector)=>int" del_cell:: "(wire=>int=>((wire)vector*((wire)vector*wire))=>((wire)vector*(wire) vector)=>bool, wire=>int=>((wire)vector*((wire)vector*wire))=>((wire)vector*(
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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 283<br />
done<br />
theorem width_ge0_int : "!! (bits::int) (n::int) (a::(wire)vector) (s::((wire)vector)<br />
vector) (d::(wire)vector). 0 ((wire)vector*((wire)vector*wire))=>((wire)vector*(wire)<br />
vector)=>int"<br />
width:: "wire=>int=>((wire)vector*((wire)vector*wire))=>((wire)vector*(wire)<br />
vector)=>int"<br />
del_cell:: "(wire=>int=>((wire)vector*((wire)vector*wire))=>((wire)vector*(wire)<br />
vector)=>bool, wire=>int=>((wire)vector*((wire)vector*wire))=>((wire)vector*(
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