Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 280 apply (auto intro: sum_ge0 maxf_ge0 sum_ge0_frange maxf_ge0_frange sum_nsub1_plusf maxf_encloses apr.height_ge0 apr.width_ge0 max2.height_ge0 max2.width_ge0 min2. height_ge0 min2.width_ge0 fork.height_ge0 fork.width_ge0 row.height_ge0 row. width_ge0) done end D.1.6 Theory lct cell theory lct_cell = or2 + eq: section {* Function definitions *} consts struct:: "int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=> bool" height:: "int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=> int" width:: "int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=>int " lct_cell:: "(int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector)) =>bool, int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=> int)block" defs struct_def: "struct == % bits ((f, a), s) (d, (f2, a2)). EX (a_eq_s::wire). (a2 = a) & (d = f) & Def ((a, s) ;;; eq $ bits ;;; a_eq_s) & Def ((a_eq_s, f) ;;; or2 ;;; f2)" height_def: "height == % bits ((f, a), s) (d, (f2, a2)). let a_eq_s = (THE ( a_eq_s::wire). (a2 = a) & (d = f) & Def ((a, s) ;;; eq $ bits ;;; a_eq_s) & Def ((a_eq_s, f) ;;; or2 ;;; f2)) in max (Height ((a_eq_s, f) ;;; or2 ;;; f2) ) ((max ((Height ((a_eq_s, f) ;;; or2 ;;; f2)) + (Height ((a, s) ;;; eq $ bits ;;; a_eq_s))) 0))" width_def: "width == % bits ((f, a), s) (d, (f2, a2)). let a_eq_s = (THE (a_eq_s ::wire). (a2 = a) & (d = f) & Def ((a, s) ;;; eq $ bits ;;; a_eq_s) & Def (( a_eq_s, f) ;;; or2 ;;; f2)) in max (Width ((a_eq_s, f) ;;; or2 ;;; f2)) ((max (Width ((a, s) ;;; eq $ bits ;;; a_eq_s)) 0))" lct_cell_def: "lct_cell == (| Def = struct, Height = height, Width = width |)" declare width_def [simp] declare height_def [simp] declare struct_def [simp] section {* Validity <strong>of</strong> width and height functions *} theorem height_ge0_int : "!! (bits::int) (f::wire) (a::(wire)vector) (s::(wire)vector ) (d::wire) (f2::wire) (a2::(wire)vector). 0
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 281 apply (auto intro: sum_ge0 maxf_ge0 sum_ge0_frange maxf_ge0_frange z_aleq_bc eq. height_ge0 eq.width_ge0 or2.height_ge0 or2.width_ge0 simp add: Let_def max_def) done section {* Additional simplification rules for different representations *} theorem height_ge0: "!! (bits::int) (f::wire) (a::(wire)vector) (s::(wire)vector) (d ::wire) (f2::wire) (a2::(wire)vector). 0
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 109 opera
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 115 const
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CHAPTER 5. SPECIALISATION 117 block
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 121 Buffe
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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