Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 280
apply (auto intro: sum_ge0 maxf_ge0 sum_ge0_frange maxf_ge0_frange sum_nsub1_plusf
maxf_encloses apr.height_ge0 apr.width_ge0 max2.height_ge0 max2.width_ge0 min2.
height_ge0 min2.width_ge0 fork.height_ge0 fork.width_ge0 row.height_ge0 row.
width_ge0)
done
end
D.1.6 Theory lct cell
theory lct_cell = or2 + eq:
section {* Function definitions *}
consts
struct:: "int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=>
bool"
height:: "int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=>
int"
width:: "int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=>int
"
lct_cell:: "(int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))
=>bool, int=>((wire*(wire)vector)*(wire)vector)=>(wire*(wire*(wire)vector))=>
int)block"
defs
struct_def: "struct == % bits ((f, a), s) (d, (f2, a2)). EX (a_eq_s::wire). (a2 =
a) & (d = f) & Def ((a, s) ;;; eq $ bits ;;; a_eq_s) & Def ((a_eq_s, f) ;;;
or2 ;;; f2)"
height_def: "height == % bits ((f, a), s) (d, (f2, a2)). let a_eq_s = (THE (
a_eq_s::wire). (a2 = a) & (d = f) & Def ((a, s) ;;; eq $ bits ;;; a_eq_s) &
Def ((a_eq_s, f) ;;; or2 ;;; f2)) in max (Height ((a_eq_s, f) ;;; or2 ;;; f2)
) ((max ((Height ((a_eq_s, f) ;;; or2 ;;; f2)) + (Height ((a, s) ;;; eq $
bits ;;; a_eq_s))) 0))"
width_def: "width == % bits ((f, a), s) (d, (f2, a2)). let a_eq_s = (THE (a_eq_s
::wire). (a2 = a) & (d = f) & Def ((a, s) ;;; eq $ bits ;;; a_eq_s) & Def ((
a_eq_s, f) ;;; or2 ;;; f2)) in max (Width ((a_eq_s, f) ;;; or2 ;;; f2)) ((max
(Width ((a, s) ;;; eq $ bits ;;; a_eq_s)) 0))"
lct_cell_def: "lct_cell == (| Def = struct, Height = height, Width = width |)"
declare width_def [simp]
declare height_def [simp]
declare struct_def [simp]
section {* Validity of width and height functions *}
theorem height_ge0_int : "!! (bits::int) (f::wire) (a::(wire)vector) (s::(wire)vector
) (d::wire) (f2::wire) (a2::(wire)vector). 0