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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 279<br />

width_def: "width == % bits n (a, b) c. Width ((a, b) ;;; row $ (n, fork ;; [[<br />

min2 $ bits, max2 $ bits ]]) ;; apr $ n ;;; c)"<br />

insert_def: "insert == (| Def = struct, Height = height, Width = width |)"<br />

declare width_def [simp]<br />

declare height_def [simp]<br />

declare struct_def [simp]<br />

section {* Validity <strong>of</strong> width and height functions *}<br />

theorem height_ge0_int : "!! (bits::int) (n::int) (a::(wire)vector) (b::((wire)vector<br />

)vector) (c::((wire)vector)vector). 0

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