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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 278<br />

qs480>, a, b) ;;; and3 ;;; match)))) 0)))"<br />

apply (auto intro: sum_ge0 maxf_ge0 sum_ge0_frange maxf_ge0_frange sum_nsub1_plusf<br />

maxf_encloses and3.height_ge0 and3.width_ge0 simp add: and3_def)<br />

apply (simp add: maxf_lamx_top)<br />

done<br />

section {* Intersection theorems *}<br />

theorem "!! (n::int) (a::(wire)vector) (b::(wire)vector) (c::wire). [| match =<br />

bool2wire True ; ALL (j::int). ((0 <br />

ALL (j::int) (j’::int). ((0 <br />

int"<br />

width:: "int=>int=>((wire)vector*((wire)vector)vector)=>((wire)vector)vector=>int<br />

"<br />

insert:: "(int=>int=>((wire)vector*((wire)vector)vector)=>((wire)vector)vector=><br />

bool, int=>int=>((wire)vector*((wire)vector)vector)=>((wire)vector)vector=><br />

int)block"<br />

defs<br />

struct_def: "struct == % bits n (a, b) c. Def ((a, b) ;;; row $ (n, fork ;; [[<br />

min2 $ bits, max2 $ bits ]]) ;; apr $ n ;;; c)"<br />

height_def: "height == % bits n (a, b) c. Height ((a, b) ;;; row $ (n, fork ;; [[<br />

min2 $ bits, max2 $ bits ]]) ;; apr $ n ;;; c)"

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