Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 276 ;;; mux $ bits $ a_geq_b ;;; c) |] ==> ALL (j::int) (j’::int). ((0 ((wire)vector*(wire) vector)=>wire=>int)block" defs struct_def: "struct == % n (a, b) c. EX (match::(wire)vector). (match = bool2wire True) & (ALL (j::int). ((0
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 277 j>, a, b) ;;; and3 ;;; match)) & (c = match)" height_def: "height == % n (a, b) c. let match = (THE (match::(wire)vector). ( match = bool2wire True) & (ALL (j::int). ((0 ) ;;; and3 ;;; match)))) 0" width_def: "width == % n (a, b) c. let match = (THE (match::(wire)vector). (match = bool2wire True) & (ALL (j::int). ((0
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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 277<br />
j>, a, b) ;;; and3 ;;; match)) & (c = match)"<br />
height_def: "height == % n (a, b) c. let match = (THE (match::(wire)vector). (<br />
match = bool2wire True) & (ALL (j::int). ((0 ) ;;; and3 ;;; match)))) 0"<br />
width_def: "width == % n (a, b) c. let match = (THE (match::(wire)vector). (match<br />
= bool2wire True) & (ALL (j::int). ((0
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