Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 274 D.1.3 Theory min2 theory min2 = mux + comp_lut: section {* Function definitions *} consts struct:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>bool" height:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>int" width:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>int" min2:: "(int=>((wire)vector*(wire)vector)=>(wire)vector=>bool, int=>((wire)vector *(wire)vector)=>(wire)vector=>int)block" defs struct_def: "struct == % bits (a, b) c. EX (a_geq_b::(wire)vector). (a_geq_b = bool2wire True) & (ALL (j::int). ((0
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 275 theorem height_ge0: "!! (bits::int) (a::(wire)vector) (b::(wire)vector) (c::(wire) vector). 0
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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 275<br />
theorem height_ge0: "!! (bits::int) (a::(wire)vector) (b::(wire)vector) (c::(wire)<br />
vector). 0
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