Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 271
}
(s, control) ; compactor clk bits n ; s2 at (0,0).
block filter core (int n, int bits) (wire clk) (wire newval[bits ], wire s[n][ bits ]) ∼
(‘t s2[n][ bits ], ‘t median[bits]) →
fst (fork ; fst (rcomp (n, map (bits, fd clk)))) ;
below ( nextstate clk bits n , insert median bits n) ;
snd pi2.
/∗∗ Median filter, ”n” + 1 size window for ”bits” bit values.
@input n Window size
@input bits Number of bits in data values
@input clk Clock signal
@input newval Current input value
@output median Current output (median) value
∗/
block filter (int n, int bits) (wire clk) (‘t newval) ∼ (‘t median)
→ loop ( filter core (n, bits) clk).
D.1.2 Theory max2
theory max2 = mux + comp_lut:
section {* Function definitions *}
consts
struct:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>bool"
height:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>int"
width:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>int"
max2:: "(int=>((wire)vector*(wire)vector)=>(wire)vector=>bool, int=>((wire)vector
*(wire)vector)=>(wire)vector=>int)block"
defs
struct_def: "struct == % bits (a, b) c. EX (a_geq_b::(wire)vector). (a_geq_b =
bool2wire True) & (ALL (j::int). ((0