Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 270 /∗∗ Locater block determines which value of the state should be discarded. @input bits Number of input bits @input n Size of state array @input a Value to look for @input s State array to look in @output d Array of true|false values to control the mode for the compactor ∗/ block locater (int bits) (int n) (‘t a, ‘t s[n+1]) ∼ (wire d[n+1]) { wire found. found = false. ((found, a), s) ; row (n+1, lct cell bits) ; pi1 ; d at (0,0). } /∗∗ Compactor cell. Operates in shift or through mode. Shift means we haven’t yet encountered the value to remove, through mode means we have. In shift mode we push the current value to the left and output the last value. In through mode we destroy the last value and output this value directly , which will also be done by all subsequent nodes ∗/ block del cell (wire clk) (int bits) (‘t x, (‘t y, wire mode)) ∼ (‘t m, ‘t n) { (y, x) ; mux bits mode ;n at (0,0). (x, y) ; mux ff clk bits mode ;m at (1,0). } /∗∗ Compactor block takes a state of size n+1 and discards the specified element to produce a new state of size n. @input n Desired size of state array @input s State array to look in @input d Array of true|false values for whether this index is the value to be removed @output s2 Output state ∗/ block compactor (wire clk) (int bits) (int n) (‘t s[n+1], wire d[n+1]) ∼ (‘t s2[n]) { (s [0], (s[n.. 1], d[n..1])) ; [id, zip 2] ; row (n, del cell clk bits) ; pi1 ; s2 at (0,0). } /∗∗ Take the median element ∗/ block midelem (int n) (‘t a[n]) ∼ (‘t b) { assert (n mod 2 == 1) ”Can’t take the middle element of an even number!”. b = a[n / 2]. } /∗∗ Insert new value into block, then extract the median ∗/ block insert median (int bits) (int n) (‘t a, ‘t b[n]) ∼ (‘t c[n+1], ‘t d) → insert bits n ; fork ; snd (midelem (n+1)). /∗∗ Remove element a from state s to produce state s2. Throw away d ∗/ block nextstate (wire clk) (int bits) (int n) (‘t a, ‘t s[n+1]) ∼ (‘t s2[n], bool d) { wire control[n+1]. (a, s) ; locater bits n ; control at (0, height((s, control) ; compactor clk bits n ; s2)).
APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 271 } (s, control) ; compactor clk bits n ; s2 at (0,0). block filter core (int n, int bits) (wire clk) (wire newval[bits ], wire s[n][ bits ]) ∼ (‘t s2[n][ bits ], ‘t median[bits]) → fst (fork ; fst (rcomp (n, map (bits, fd clk)))) ; below ( nextstate clk bits n , insert median bits n) ; snd pi2. /∗∗ Median filter, ”n” + 1 size window for ”bits” bit values. @input n Window size @input bits Number of bits in data values @input clk Clock signal @input newval Current input value @output median Current output (median) value ∗/ block filter (int n, int bits) (wire clk) (‘t newval) ∼ (‘t median) → loop ( filter core (n, bits) clk). D.1.2 Theory max2 theory max2 = mux + comp_lut: section {* Function definitions *} consts struct:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>bool" height:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>int" width:: "int=>((wire)vector*(wire)vector)=>(wire)vector=>int" max2:: "(int=>((wire)vector*(wire)vector)=>(wire)vector=>bool, int=>((wire)vector *(wire)vector)=>(wire)vector=>int)block" defs struct_def: "struct == % bits (a, b) c. EX (a_geq_b::(wire)vector). (a_geq_b = bool2wire True) & (ALL (j::int). ((0
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APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 270<br />
/∗∗ Locater block determines which value <strong>of</strong> the state should be discarded.<br />
@input bits Number <strong>of</strong> input bits<br />
@input n Size <strong>of</strong> state array<br />
@input a Value to look for<br />
@input s State array to look in<br />
@output d Array <strong>of</strong> true|false values to control the mode for the compactor<br />
∗/<br />
block locater (int bits) (int n) (‘t a, ‘t s[n+1]) ∼ (wire d[n+1]) {<br />
wire found.<br />
found = false.<br />
((found, a), s) ;<br />
row (n+1, lct cell bits) ;<br />
pi1 ;<br />
d at (0,0).<br />
}<br />
/∗∗ Compactor cell. Operates in shift or through mode. Shift means we<br />
haven’t yet encountered the value to remove, through mode means we<br />
have. In shift mode we push the current value to the left and output<br />
the last value. In through mode we destroy the last value and output<br />
this value directly , which will also be done by all subsequent nodes<br />
∗/<br />
block del cell (wire clk) (int bits) (‘t x, (‘t y, wire mode)) ∼ (‘t m, ‘t n) {<br />
(y, x) ; mux bits mode ;n at (0,0).<br />
(x, y) ; mux ff clk bits mode ;m at (1,0).<br />
}<br />
/∗∗ Compactor block takes a state <strong>of</strong> size n+1 and discards the specified<br />
element to produce a new state <strong>of</strong> size n.<br />
@input n Desired size <strong>of</strong> state array<br />
@input s State array to look in<br />
@input d Array <strong>of</strong> true|false values for whether this index is the value to<br />
be removed<br />
@output s2 Output state<br />
∗/<br />
block compactor (wire clk) (int bits) (int n) (‘t s[n+1], wire d[n+1]) ∼ (‘t s2[n]) {<br />
(s [0], (s[n.. 1], d[n..1])) ;<br />
[id, zip 2] ;<br />
row (n, del cell clk bits) ;<br />
pi1 ;<br />
s2 at (0,0).<br />
}<br />
/∗∗ Take the median element ∗/<br />
block midelem (int n) (‘t a[n]) ∼ (‘t b) {<br />
assert (n mod 2 == 1) ”Can’t take the middle element <strong>of</strong> an even number!”.<br />
b = a[n / 2].<br />
}<br />
/∗∗ Insert new value into block, then extract the median ∗/<br />
block insert median (int bits) (int n) (‘t a, ‘t b[n]) ∼ (‘t c[n+1], ‘t d)<br />
→ insert bits n ; fork ; snd (midelem (n+1)).<br />
/∗∗ Remove element a from state s to produce state s2. Throw away d ∗/<br />
block nextstate (wire clk) (int bits) (int n) (‘t a, ‘t s[n+1]) ∼ (‘t s2[n], bool d) {<br />
wire control[n+1].<br />
(a, s) ; locater bits n ; control at (0, height((s, control) ; compactor clk bits n ; s2)).